Multi-controller Inspection System for Semiconductor Defect Detection
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Solution Overview
Problem
Conventional defect inspection systems in semiconductor wafers and masks face challenges in detecting defects efficiently due to computational intensity and the need for disruptive changes in fully-deployed production systems, leading to delayed adoption of new algorithms and technologies.
Innovation Solution
A distributed heterogeneous computer system employing shared memory and multiple defect-inspection algorithms, where general-purpose and targeted algorithms are used in conjunction with flexible sampling to match data processing rates, allowing for efficient defect detection without disrupting existing image acquisition systems.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If multiple defect-inspection algorithms are applied to improve defect detection capability, then detection precision is improved, but computational complexity and processing time increase
Solution Approach 1:
The patent divides the image data processing into multiple independent algorithms that can be executed in parallel. Each algorithm processes different aspects of defect detection simultaneously, reducing overall processing time while maintaining comprehensive detection capability across multiple defect types.
Solution Approach 2:
The patent introduces a multi-dimensional processing approach by utilizing both CPU and GPU architectures simultaneously. The CPU handles general-purpose algorithms while the GPU accelerates computationally intensive targeted algorithms, effectively adding a computational dimension that speeds up processing without sacrificing detection precision.
2Measurement precision
If new defect-inspection algorithms are introduced to improve detection capability, then measurement precision is improved, but device complexity increases
Solution Approach 1:
The patent creates a universal processing framework that can accommodate multiple different defect-inspection algorithms through a common interface. This multi-functional architecture allows various algorithms to be integrated without proportionally increasing system complexity, as they all operate within the same standardized environment.
Solution Approach 2:
The shared memory acts as an intermediary component that simplifies the integration of multiple algorithms. By providing a common data exchange interface, the shared memory reduces the complexity of inter-algorithm communication and data management, allowing algorithms to be added without proportionally increasing system complexity.
3Measurement precision
If full sampling of image data is performed to ensure complete defect detection, then measurement precision is improved, but productivity decreases
Solution Approach 1:
The patent applies different sampling strategies to different algorithms based on their specific requirements. While the host image module performs full sampling for comprehensive coverage, secondary image modules can use reduced sampling where appropriate, achieving sufficient detection precision while improving overall inspection throughput.
4Measurement precision
If computational resources are increased to handle complex algorithms, then measurement precision is improved, but loss of energy increases
Solution Approach 1:
The patent replaces traditional CPU-based processing with GPU-accelerated computing for certain algorithms. This substitution leverages the parallel processing capabilities of GPUs, which can perform complex computations more energy-efficiently than traditional sequential CPU processing, thereby reducing energy loss while maintaining or improving detection precision.
Data Source
AI summary
An inspection system is disclosed. The inspection system includes a shared memory configured to receive image data from a defect inspection tool and a controller communicatively coupled to the shared memory. The controller includes a host image module configured to apply one or more general-purpose defect-inspection algorithms to the image data using central-processing unit (CPU) architectures, a results module configured to generate inspection data for defects identified by the host image module, and secondary image module(s) configured to apply one or more targeted defect-inspection algorithms to the image data. The secondary image module(s) employ flexible sampling of the image data to match a data processing rate of the host image module within a selected tolerance. The flexible sampling of the image data is adjusted responsive to the inspection data generated by the results module and the host image module.


