Multi-Controller Memory Architecture for Parallel Data Access
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Solution Overview
Problem
In multi-processor architectures, the common AXI bus causes conflicts during concurrent data operations, leading to decreased processor utilization and increased power consumption due to limited access efficiency.
Innovation Solution
A multi-controller multi-memory device is configured with multiple controllers and memory units interconnected via arbitration, request-distribution, and read-selection units, utilizing request-submission and response-transmission channels to enable parallel data reading and writing, allowing concurrent access and reducing conflicts through arbitration and priority ranking.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a common AXI bus is used for data access, then system simplicity is maintained, but data access efficiency deteriorates due to conflicts among concurrent operations
Solution Approach 1:
The patent divides the single common AXI bus into multiple independent data access channels, each capable of concurrent operation. This segmentation allows multiple processors to access memory simultaneously through different channels, eliminating the bottleneck of the shared bus while maintaining relative simplicity through modular architecture.
Solution Approach 2:
The patent introduces arbitration units as intermediary components that manage and coordinate access requests across multiple channels. These arbitration units mediate between processors and memory resources, enabling efficient conflict resolution and resource allocation without requiring a single shared bus, thus improving data access efficiency.
2Device complexity
If processors share a common AXI bus, then hardware resources are reduced, but processor utilization deteriorates due to access conflicts
Solution Approach 1:
The system segments the shared bus architecture into multiple dedicated data access channels, allowing each processor to utilize its own channel for memory access. This segmentation ensures that processor operations proceed without mutual interference, maintaining high processor utilization while using hardware resources efficiently through parallel channel operation.
Solution Approach 2:
The patent implements dynamic resource allocation where data access channels and arbitration units are actively managed based on real-time processor needs. This dynamic approach allows the system to adapt resource distribution to current workload demands, ensuring optimal processor utilization without requiring excessive static hardware resources.
3Productivity
If concurrent data operations are allowed on a common AXI bus, then throughput is improved, but power consumption increases due to conflict resolution overhead
Solution Approach 1:
By segmenting the bus into multiple independent data access channels, the patent enables true parallel concurrent operations without conflicts. Each channel operates independently, allowing simultaneous data transfers that increase throughput while minimizing the power consumption associated with conflict resolution arbitration.
Solution Approach 2:
The patent ensures continuous useful action by maintaining always-active data access channels that can operate concurrently without interruption from conflict resolution. This continuous operation maximizes throughput while reducing the energy waste that would occur during bus arbitration and conflict handling in shared architectures.
Data Source
AI summary
A multi-controller multi-memory device is disclosed. The device may include a plurality of controllers and a plurality memory units (m-units). Each controller is connected with a dedicated request-distribution unit (dist-unit) and a dedicated read-selection unit (read-unit). Each m-unit is connected with a dedicated arbitration unit (abt-unit). A controller's dedicated dist-unit is coupled with each of the abt-units dedicated to the plurality of m-units. The controller is configured to transmit a data-request to the controller's dedicated dist-unit, the data-request addressing an m-unit. The controller's dedicated dist-unit is configured to transmit the data-request to an abt-unit dedicated to the m-unit. The abt-unit is configured to select the data-request for transmitting to the m-unit based on an arbitration process.