Multi-core Processor Address Allocator for Inter-Core Communication
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Solution Overview
Problem
Multi-core processors face performance degradation due to increased computational overhead from frequent address translation operations during inter-process communication (IPC) between cores, which hampers data processing efficiency.
Innovation Solution
A multi-core processor design that includes a shared memory with a message queue and address allocators, which perform address translation operations based on an access count to reduce the frequency of address translations, allowing cores to access memory regions in sequence and thereby minimize computational burden.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If address translation operations are performed frequently during inter-process communication between cores, then data can be accessed in shared memory, but computational overhead increases and processing efficiency decreases
Solution Approach 1:
The patent applies preliminary action by pre-establishing address mapping relationships between message queue memory regions and shared memory regions before inter-process communication occurs. The address allocator pre-translates and stores mapping information, so that during actual IPC operations, cores can directly use pre-computed addresses without performing address translation operations, thereby eliminating computational overhead and instruction cycle delays.
2Ease of operation
If multiple memory regions are accessed sequentially in message queues, then inter-process communication can be performed, but frequent address translation operations increase computational burden
Solution Approach 1:
The patent introduces an address allocator as an intermediary component between cores and shared memory. The address allocator maintains and manages address mapping tables that translate logical addresses from message queue operations into physical addresses in shared memory. This intermediary handles all address translation operations centrally, allowing cores to perform simple sequential memory accesses without bearing the computational burden of address translation, thus simplifying the overall system operation while maintaining full IPC functionality.
Data Source
AI summary
A multi-core processor includes a plurality of cores, a shared memory, a plurality of address allocators, and a bus. The shared memory has a message queue including a plurality of memory regions for transmitting messages between the plurality of cores. The plurality of address allocators are configured to, each time addresses in a predetermined range corresponding to a reference memory region among the plurality of memory regions are received from a corresponding core among the plurality of cores, control the plurality of memory regions to be accessed in sequence by applying an offset determined according to an access count of the reference memory region to the addresses in the predetermined range. The bus is configured to connect the plurality of cores, the shared memory, and the plurality of address allocators to one another.