Multi-Core Processor Status Detection via Dynamic BIST
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Solution Overview
Problem
In multi-core processor architectures, existing methods are inefficient in dynamically detecting and identifying failing cores in real-time within a built-in self-test (BIST) environment, especially for systems with numerous cores, and struggle to determine the dominant logic state of multiple signal bits or data channels.
Innovation Solution
The implementation of a sequential and concurrent processor core status detection method that involves running a BIST on multiple cores, evaluating the pass/fail state of each core, and recording failed cores, while dynamically determining the dominant logic state through selective bus sampling and conditional dominant state gating, using a novel 'bit-swap' logic function block in a cascading array structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional multi-processor test techniques are used for large numbers of cores, then testing can be performed, but efficiency deteriorates and becomes inadequate
Solution Approach 1:
The patent segments the large-scale multi-core testing problem into smaller manageable units by implementing hierarchical testing architecture. Test controllers are divided into multiple groups, each managing a subset of cores. The testing process is segmented into phases: initial quick screening of individual cores, followed by grouped functional testing, and finally system-level integration testing. This segmentation allows efficient handling of large core counts without overwhelming the test infrastructure.
Solution Approach 2:
The patent introduces a hierarchical dimension to the testing architecture, moving from flat one-to-one core-to-controller mapping to a multi-level hierarchy. Multiple cores are grouped under single test controllers, and controllers are organized in groups managed by master controllers. This dimensional change in the testing architecture enables scalable testing of large core arrays by adding organizational layers rather than increasing linear controller count.
2Speed
If all processor cores are tested concurrently, then testing speed is improved, but the ability to dynamically detect and identify failing cores in real-time deteriorates
Solution Approach 1:
The patent implements dynamic test configuration that adapts during the testing process. Test controllers can dynamically adjust their operational state based on real-time results. When a core or controller fails, the system dynamically reconfigures to exclude the failed unit and redistribute its workload to healthy units. This dynamic adaptation maintains high testing throughput while ensuring accurate failure identification through real-time monitoring and adaptive workload redistribution.
Solution Approach 2:
The patent incorporates real-time feedback mechanisms where test results from concurrent operations are immediately analyzed and fed back to the test control system. This feedback enables the system to identify failing cores during the testing process rather than only at the end. The feedback loop allows dynamic adjustment of test parameters, redistribution of test loads, and immediate exclusion of failed units, maintaining both speed and precision in failure detection.
3Measurement precision
If sequential BIST testing is performed on each core, then failure identification precision is improved, but testing time increases
Solution Approach 1:
The patent implements periodic testing cycles that alternate between individual core screening and grouped functional testing. The testing process is divided into periodic phases: quick individual core status checks, followed by periodic grouped functional tests, and periodic system-level validation. This periodic structure allows the system to maintain precise failure identification through individual testing while reducing overall testing time through efficient grouping and parallel execution of periodic test cycles.
Solution Approach 2:
The patent applies preliminary action by performing quick individual core screening tests before committing to more time-consuming grouped functional tests. This preliminary screening identifies obviously failed cores that can be immediately excluded, preventing waste of time on obviously defective units during subsequent detailed testing phases. The preliminary action filters the test population, allowing more efficient allocation of testing resources to potentially functional cores.
4Productivity
If failed cores continue to participate in testing, then testing completeness is maintained, but power consumption increases and testing efficiency deteriorates
Solution Approach 1:
The patent implements a mechanism to discard failed cores from active testing participation once they are identified. When a core or controller fails, the system discards its participation in subsequent test operations and recovers its test workload by redistributing it to healthy cores and controllers. This discarding and recovering process maintains testing completeness by ensuring all cores are initially tested, while improving efficiency and reducing power consumption by excluding failed units from ongoing testing operations.
Data Source
AI summary
Exemplary embodiments include a sequential and concurrent status detection and evaluation method for multiple processor cores, including receiving data from a plurality of processor cores, for each of the plurality of processor cores, simultaneously running a built-in self test to determine if each of the plurality of cores has failed, checking the data for a dominant logic state and recording a subset of the plurality of processor cores that have failed.