Multi-core Interconnection Bus Request Forwarding
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Solution Overview
Problem
Existing multi-core processor inter-core data forwarding methods are inefficient due to long data transmission paths and potential transmission congestion, leading to delayed data return to the initiating processor core.
Innovation Solution
The multi-core processor incorporates a multi-core interconnection bus with request processing interfaces and a request storage unit that allows direct forwarding of read data requests and results between processor cores, bypassing the need for intermediate storage, thereby reducing transmission delays and increasing data forwarding speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If data is forwarded through the request storage unit, then data consistency is maintained, but transmission delay increases
Solution Approach 1:
The patent segments the data forwarding path into two types: shared data paths that go through the request storage unit to maintain consistency, and non-shared data paths that can use direct forwarding to reduce delay. This segmentation allows the system to optimize for both reliability and speed by routing different types of data through appropriate paths.
Solution Approach 2:
The patent changes the forwarding parameter based on data sharing status. When data is determined to be non-shared, the system switches from the conservative request storage unit path to the faster direct forwarding path, effectively changing the transmission parameter to optimize for speed without compromising consistency for shared data.
2Reliability
If the request storage unit handles all requests, then data consistency is ensured, but transmission congestion occurs
Solution Approach 1:
The patent segments the request handling workload by identifying which requests can be processed directly without going through the request storage unit. Non-shared data requests are handled through direct forwarding paths, while only shared data requests use the request storage unit, thereby segmenting the traffic to prevent congestion.
Solution Approach 2:
The patent introduces an intermediary mechanism (the determination unit) that identifies whether data is shared or non-shared before routing the request. This intermediary allows the system to bypass the request storage unit for non-shared data, reducing its workload and preventing congestion while maintaining consistency for shared data.
3Productivity
If direct forwarding is used, then transmission speed increases, but data consistency may be compromised
Solution Approach 1:
The patent introduces a determination unit as an intermediary that assesses whether data is shared or non-shared before allowing direct forwarding. This intermediary ensures that direct forwarding (which provides speed) is only used when it won't compromise consistency, i.e., for non-shared data.
Solution Approach 2:
The patent dynamically changes the forwarding parameter based on the shared status of the data. When data is determined to be non-shared, the system enables direct forwarding for speed; when shared data is detected, the system switches to the request storage unit path to maintain consistency, thus adaptively changing parameters to balance speed and reliability.
Data Source
AI summary
The present invention discloses a multi-core processor and an inter-core data forwarding method. The multi-core processor includes a plurality of processor cores and a multi-core interconnection bus. The multi-core interconnection bus includes: a plurality of request processing interfaces, each of which is adapted to receive a read data request sent by a coupled processor core, and send the read data request to a request storage unit; and the request storage unit, adapted to receive the read data request sent by the request processing interface, and forward the read data request to another request processing interface, where the request processing interface receives a read data request forwarded by the request storage unit, sends the read data request to the coupled processor core, receives a request result that is returned by the processor core by reading a cache of the processor core, and sends the request result to a request processing interface coupled to a processor core that initiates the request; and receives a request result sent by the another request processing interface, determines valid data based on the received request result, and sends the valid data to the coupled processor core.