Multi-core clocking with anti-freeze isolation
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Solution Overview
Problem
In multi-core processor systems, simultaneous clock disturbances can affect all processor cores, leading to system instability and safety risks in applications like vehicle brakes and steering systems, as existing solutions either share common components or rely on redundant clock sources that can be affected by the same disturbances.
Innovation Solution
A clocking system that uses a clock control circuit to generate and distribute clock signals to multiple processor cores independently, allowing one core to be clocked while freezing others, using a finite state machine to manage duty cycles and prevent simultaneous disturbances, and a watchdog mechanism to detect and mitigate clock signal disturbances.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If redundant clock sources are used to provide reliable clock signals for multiple data processing devices, then clock reliability is improved, but the system can still be affected by the same disturbance event since shared elements (power supply, clock distribution network) are common to both sources
Solution Approach 1:
The system segments the clock distribution by creating separate clock domains for different processor cores. Each core has its own clock control circuit that can independently control its clock signal, preventing a single disturbance from affecting all cores simultaneously. The clock network is divided into isolated segments with dedicated control for each segment.
Solution Approach 2:
A clock control circuit acts as an intermediary between the clock source and processor cores. This intermediary includes monitoring circuitry that detects clock disturbances and can freeze or disable affected cores, preventing disturbances from propagating to all cores. The intermediary provides isolation and protective control between the clock source and the cores.
2Device complexity
If the same clock source is used for all processor cores to simplify the system, then device complexity is reduced, but a single disturbance event can affect multiple cores simultaneously causing system instability
Solution Approach 1:
The system dynamically adjusts clock signal distribution based on detected disturbances. The clock control circuit monitors clock signals and dynamically freezes or disables affected cores by blocking their clock signals while preserving clocks for unaffected cores. This dynamic response maintains system stability without requiring permanently complex redundant clock distributions.
3Reliability
If additional monitoring circuitry is added to detect clock disturbances and reset or freeze the system, then system reliability is improved, but device complexity increases due to the additional circuitry required for each core
Solution Approach 1:
The clock control circuit performs multiple functions: it generates clock signals, monitors for disturbances, freezes affected cores, and coordinates with other clock control circuits. This multi-functional approach consolidates monitoring and control capabilities into existing clock distribution infrastructure rather than adding separate dedicated monitoring circuitry for each core.
Data Source
AI summary
A clocking system, comprises a plurality of clocked data processing devices and a clock control circuit controlling a generation of a plurality of clock signals and an application of the clock signals to the plurality of data processing devices, allowing to clock at least one of the data processing devices while freezing all but the at least one of the data processing devices. A method for clocking a plurality of clocked data processing devices comprises controlling a generation of a plurality of clock signals and controlling an application of the clock signals to the plurality of data processing devices, allowing to clock at least one of the data processing devices while freezing all but the at least one of the data processing devices.