Multi-core Coherency via Memory Order Buffer Segmentation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In multiprocessor systems, the existing coherency schemes are inefficient due to high power consumption and resource expenses caused by snoop transactions across multiple cache levels for shared data, especially in systems with a write-invalidate protocol.
Innovation Solution
Implementing a shared memory order buffer and a common last-level cache that distinguishes between coherent and non-coherent store transactions, allowing non-coherent transactions to bypass lower-level caches and reducing the need for cache coherency checks, thereby optimizing power consumption and die area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a write-invalidate protocol is used with multiple cache levels, then cache coherency is maintained, but power consumption and resource usage increase due to snoop transactions
Solution Approach 1:
The patent segments the cache coherency handling by introducing a memory order buffer (MOB) that separates coherent and non-coherent store transactions. The MOB acts as an intermediary that filters and directs transactions appropriately, preventing unnecessary snoop transactions from reaching lower-level caches. This segmentation allows the system to maintain coherency for coherent transactions while avoiding the power consumption associated with snooping non-coherent transactions.
Solution Approach 2:
The memory order buffer serves as an intermediary component between processor cores and the last-level cache. It receives store transactions from processor cores, determines whether they are coherent or non-coherent, and only forwards coherent transactions to the last-level cache. This intermediary function eliminates the need for lower-level caches to participate in coherency protocols, thereby reducing power consumption while maintaining reliability.
2Reliability
If snoop transactions are performed across multiple cache levels, then cache coherency is ensured, but die area and resource expenses increase
Solution Approach 1:
The patent extracts the coherency management function from lower-level caches and concentrates it in the memory order buffer and last-level cache. By taking out the coherency protocol handling from individual cache levels, the system eliminates redundant coherency logic in lower-level caches, reducing die area while maintaining coherency through the centralized MOB and last-level cache architecture.
Solution Approach 2:
The memory order buffer performs multiple functions: it acts as a store buffer, filters coherent from non-coherent transactions, maintains memory ordering, and manages coherency protocols. This multi-functionality consolidates what would otherwise require separate components in each cache level, reducing overall die area while ensuring coherency.
3Reliability
If coherent store transactions are processed through lower-level caches, then cache coherency is maintained, but performance decreases due to unnecessary coherency checks
Solution Approach 1:
The memory order buffer performs preliminary classification of store transactions into coherent and non-coherent categories before they reach the last-level cache. By预先 determining which transactions require coherency handling, the system avoids unnecessary coherency checks in the cache hierarchy, improving performance while maintaining coherency for transactions that require it.
Solution Approach 2:
Non-coherent store transactions are made to skip through the cache coherency protocol machinery entirely by being identified and directed by the memory order buffer. These transactions rush through the system without triggering snoop operations or coherency checks, improving performance by eliminating unnecessary processing steps while coherent transactions receive the appropriate coherency treatment.
Data Source
Figure 1A
Figure 1B
Figure 2
AI summary
A special class of loads and stores access a user-defined memory region where coherency and memory orders are only enforced at the coherent point. Coherent memory requests, which are limited to user-defined memory region, are dispatched to the common memory ordering buffer. Non-coherent memory requests (e.g., all other memory requests) can be routed via non-coherent lower level caches to the shared last level cache. By assigning a private, non-overlapping, address spaces to each of the processor cores, the lower-level caches do not need to implement the logic necessary to maintain cache coherency. This can reduce power consumption and integrated circuit die area. This can also improve memory bandwidth and performance for applications with predominantly non-coherent memory accesses while still providing memory coherence for specific memory range(s)/applications that demand it.