Multi-core Processor Comparison Encoding for Test Efficiency
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The increasing number of processor cores in integrated circuits complicates the testing process, as traditional serial testing methods multiply test time and I/O pins, making it inefficient to test multiple cores effectively.
Innovation Solution
A multi-core processor microchip with comparison circuitry and an encoding module that assigns additional binary bits to processor cores, allowing for on-chip comparison and encoding of test data, reducing the volume of data transferred and enabling efficient detection of faults across multiple cores.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If serial testing is used for each processor core, then each core can be tested individually, but test time is multiplied according to the number of cores
Solution Approach 1:
The patent merges the testing of multiple processor cores by implementing a shared test input/output interface that can simultaneously access multiple cores through multiplexing. The test architecture combines multiple core test sequences into a single integrated test framework, allowing parallel evaluation of multiple cores without requiring separate dedicated test paths for each core, thereby reducing overall test time while maintaining comprehensive coverage.
Solution Approach 2:
The patent creates a universal test interface that serves multiple processor cores with a single set of test inputs and outputs. The test architecture is designed so that the same physical I/O pins and test circuitry can be dynamically configured to test different cores through software-controlled multiplexing, eliminating the need for duplicate test infrastructure for each core and significantly reducing test time.
2Productivity
If duplicate processor cores are included, then processing capability increases, but the number of I/O pins to be tested increases
Solution Approach 1:
The patent merges the I/O pin requirements for multiple processor cores by implementing shared test infrastructure. Instead of providing separate dedicated I/O pins for each core, the design uses a common set of I/O pins that can be dynamically assigned to different cores through multiplexing logic, thereby reducing the total number of physical I/O pins needed while supporting multiple cores.
Solution Approach 2:
The patent implements a universal I/O interface that can serve multiple processor cores dynamically. The test architecture uses software-controlled multiplexing to assign the same physical I/O pins to different cores during different test phases, creating a multi-functional test system that reduces the total I/O pin count while maintaining the ability to test all cores.
3Reliability
If separate test input and test output are provided for each processor core, then each core can be tested independently, but the number of required I/O pins is multiplied
Solution Approach 1:
The patent merges the test input and output resources for multiple cores into a single shared infrastructure. The design implements multiplexed test interfaces where a single set of physical I/O pins can be dynamically assigned to different cores through software control, eliminating the need for separate dedicated I/O pins for each core while maintaining independent test capability.
Solution Approach 2:
The patent creates a universal test interface that can independently test any processor core by dynamically assigning the same physical I/O pins to different cores through software-controlled multiplexing. This multi-functional approach reduces the total number of I/O pins required while preserving the ability to perform independent testing of each core.
Data Source
AI summary
Systems and methods to test processor cores of a multi-core processor microchip are provided. Comparison circuitry may be configured to compare data output from processor cores of a microchip. An encoding module may be configured to encode received data by initially assigning binary bit values to the processor cores. Based on at least one of a number of the processor cores and a first binary bit value, a first additional binary bit may be added to the first binary bit value. The first binary bit value may be assigned to a first processor core of the plurality of processor cores.