Multi-Core Semiconductor Defect Analysis via Parallel Execution
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Solution Overview
Problem
Existing semiconductor device testing methods suffer from poor reproducibility of defects, as the environment used for debug processing differs from the actual operating environment, making it difficult to reproduce the operation speed and obtain the program that caused defects in test escapes.
Innovation Solution
A semiconductor device with multiple CPU cores that execute programs in analysis and debugging modes, allowing for comparison of arithmetic result data to generate analysis information for defect analysis, enabling high defect reproducibility without the need for non-defective samples.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If debug processing is performed using a host PC and I/F devices as in the related art, then the debugging operation can be executed, but the actual operation speed of test escapes cannot be reproduced and the program that generated the defect cannot be obtained
Solution Approach 1:
The patent creates a copy of the actual operating environment within the semiconductor device itself by providing an analysis mode that replicates the test escape conditions. Multiple arithmetic cores execute the same program in parallel, generating arithmetic result data that can be compared to identify defects without needing external host PCs or I/F devices, thereby achieving high defect reproducibility while eliminating complex external debugging equipment
Solution Approach 2:
The semiconductor device is designed to perform multiple functions: normal operation mode for regular processing and analysis mode for defect detection. The multiple arithmetic cores can execute both user programs and analysis programs, and the same hardware infrastructure supports both operational modes, eliminating the need for separate debugging equipment and achieving environment consistency between testing and actual operation
2Reliability
If multiple arithmetic cores execute programs in analysis mode comparing arithmetic result data, then high defect reproducibility is achieved, but the device complexity increases
Solution Approach 1:
The patent divides the semiconductor device into multiple independent arithmetic cores, each capable of executing programs independently. This segmentation allows parallel execution of the same program across multiple cores, generating multiple sets of arithmetic result data that can be compared to detect defects. The segmented architecture achieves high defect detection accuracy while maintaining modular simplicity
Solution Approach 2:
The patent combines multiple arithmetic cores and their associated local memory areas into a unified semiconductor device structure that operates in coordination during analysis mode. The cores share common control logic and can access shared resources, merging their functionalities to achieve defect detection through comparison of their arithmetic results, thereby improving reliability without proportionally increasing overall device complexity
Data Source
AI summary
Related semiconductor devices have a problem in which analysis processing with high defect reproducibility cannot be performed. According to an embodiment, a semiconductor device includes a first arithmetic core that executes a first program stored in a first code area using a first local memory area and a second arithmetic core that executes a second program stored in a second code area using a second local memory area. In an analysis mode, the semiconductor device performs first analysis processing that causes both the first arithmetic core and the second arithmetic core to execute the first program and second analysis processing that causes both the first arithmetic core and the second arithmetic core to execute the second program, and compares a plurality of arithmetic result data pieces acquired from the first and second analysis processing to thereby acquire analysis information used for defect analysis.