Multi-core Processor Distributed Work Sharing via Virtual Queues
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Solution Overview
Problem
Current multi-core processors in communication networks face limitations in processing speed due to centralized work distribution mechanisms, where data packet steering is restricted by the processing speed of a single core, and require additional instruction cycles and hardware for efficient distribution among multiple cores.
Innovation Solution
A distributed work sharing mechanism is implemented using virtual queues and interrupt signals to allow multiple idle cores to process data packets simultaneously, eliminating the need for centralized packet steering and additional hardware, thereby enhancing processing speed without classification and steering overheads.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If centralized packet steering is used to distribute data packets among multiple cores, then work distribution is achieved, but processing speed is limited by the speed of a single core and additional instruction cycles are required
Solution Approach 1:
The patent extracts the packet steering function from the software domain and implements it in hardware using a content addressable memory (CAM). The CAM directly matches packet characteristics with core assignments, eliminating the need for software-based classification and steering instruction cycles. This extraction of the steering function to hardware resolves the contradiction by enabling both automated work distribution and high-speed processing simultaneously.
Solution Approach 2:
The patent introduces a hardware intermediary (CAM-based steering mechanism) between the network interface and the core processors. This intermediary automatically performs packet classification and steering based on packet characteristics, freeing the cores from involvement in distribution decisions and enabling parallel processing without single-core bottlenecks.
2Productivity
If additional hardware is used for efficient packet distribution among cores, then processing efficiency is improved, but area overheads increase
Solution Approach 1:
The CAM structure is designed to serve multiple functions: packet classification, core assignment, and steering decision-making. By making the hardware structure multi-functional, the patent achieves high processing efficiency without requiring separate dedicated hardware for each function, thereby reducing overall area overheads while maintaining productivity gains.
3Ease of operation
If software-based packet steering is implemented, then packet classification and distribution is achieved, but additional instruction cycles are required increasing system cycle time
Solution Approach 1:
The patent replaces the software-based packet steering mechanism (which requires sequential instruction cycles) with a hardware-based CAM lookup mechanism. This substitution eliminates the time-consuming software processing steps while maintaining the packet classification and distribution functionality, directly reducing system cycle time.
Data Source
AI summary
A system for managing data packets has multiple cores, a data buffer, a hardware accelerator, and an interrupt controller. The interrupt controller transmits a first interrupt signal to a first one of the cores based on a first hardware signal received from the hardware accelerator. The first core creates a copy of buffer descriptors (BD) of a buffer descriptor ring that correspond to the data packets in the data buffer in a first virtual queue and indicates to the hardware accelerator that the data packets are processed. If there are additional data packets, the interrupt controller transmits a second interrupt signal to a second core, which performs the same steps as performed by the first core. The first and the second cores simultaneously process the data packets associated with the BDs in the first and second virtual queues, respectively.