Multi-core System DMA Descriptor for Cross-Core Data Transfer
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Solution Overview
Problem
In multi-core systems, the complexity of data sharing between processor cores leads to increased processing loads on CPUs during data transmission and reception, necessitating a simplification of the communication procedure.
Innovation Solution
A multi-core system is designed with a memory management unit (MMU) that sets a transmission descriptor based on a page number for data stored in another memory, utilizing a DMA unit to facilitate direct memory access and reduce CPU load by simplifying data transfer between processor cores.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If data is transmitted between processor cores by allocating registers or RAM of one CPU to another CPU's memory space, then the communication procedure between CPUs is simplified, but the processing load on the CPUs increases due to the complexity of managing memory allocation and data sharing
Solution Approach 1:
The patent introduces a DMA unit as an intermediary device between the processor cores and memory systems. The DMA unit autonomously manages data transfer between different memory spaces without requiring processor intervention, thus simplifying the communication procedure while reducing the processing load on the CPUs. The DMA unit handles memory allocation, data copying, and transfer coordination that would otherwise burden the processor cores.
Solution Approach 2:
The patent divides the data transfer function into separate components: the processor core generates data, the DMA unit handles the transfer, and the destination memory receives the data. This segmentation allows the processor to focus on computation while the DMA unit specializes in data movement, reducing overall system complexity and processing load on the CPUs.
2Adaptability or versatility
If page data is stored in another memory coupled to a different processor core, then data sharing between cores is enabled, but the processing complexity increases due to cross-core memory access management
Solution Approach 1:
The DMA unit is designed to autonomously manage cross-core memory access without requiring processor intervention. When page data needs to be accessed from another core's memory, the DMA unit self-manages the transfer by setting transmission descriptors, identifying source and destination addresses, and executing the data movement independently, thus enabling data sharing while reducing processing complexity.
Solution Approach 2:
The system pre-establishes memory mappings and transmission descriptors that define cross-core access paths in advance. This preliminary configuration allows the DMA unit to quickly execute data transfers without complex runtime decision-making by the processor, enabling flexible data sharing while keeping processing complexity low.
Data Source
AI summary
A multi-core system includes a first processor core, a first memory coupled to the first processor core, a first communication IF including a first DMA unit coupled to the first memory, a second processor core, a second memory coupled to the second processor core, a second communication IF including a second DMA unit coupled to the second memory, and an MMU. In a case where page data of a page designated as a read destination by the first processor core is stored in the second memory, the MMU causes the first DMA unit to set a first transmission descriptor based on a page number of the page. The first communication IF transmits a data request including the page number and destination data to the second communication IF according to the first transmission descriptor.