Multi-core Processor Dynamic Mode Switching for Fault Detection
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Solution Overview
Problem
Existing multi-core processors lack the ability to efficiently switch between operation modes to detect and correct faults, which affects their reliability and performance, especially in high-reliability applications like advanced driver assistance systems.
Innovation Solution
A multi-core processor with two operation modes: DMR (Dual-Modular Redundancy) and non-DMR, where processors can be configured to perform the same or different tasks by assigning the same or different core IDs, allowing for fault detection and correction through a manager and reset controller.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple cores perform the same task to improve reliability through redundancy, then fault detection capability is improved, but processing speed and productivity deteriorate due to redundant computations
Solution Approach 1:
The processor dynamically switches between DMR mode (for high reliability) and non-DMR mode (for high performance) based on operational requirements. This dynamic reconfiguration allows the system to optimize between fault detection capability and processing speed by changing the operational mode rather than being fixed in one state
Solution Approach 2:
The system changes the core ID assignment parameter to control operational mode. When cores are assigned the same core ID, they operate in DMR mode for fault detection; when assigned different core IDs, they operate in non-DMR mode for performance. This parameter change enables flexible transition between reliability and productivity optimization
2Productivity
If multiple cores perform different tasks to improve processing speed, then productivity is improved, but fault detection capability deteriorates due to lack of redundancy
Solution Approach 1:
The processor dynamically switches between non-DMR mode (for high performance) and DMR mode (for high reliability) based on operational requirements. This dynamic reconfiguration allows the system to optimize between processing speed and fault detection capability by changing the operational mode rather than being fixed in one state
Solution Approach 2:
The system changes the core ID assignment parameter to control operational mode. When cores are assigned different core IDs, they operate in non-DMR mode for processing speed; when assigned the same core ID, they operate in DMR mode for fault detection. This parameter change enables flexible transition between productivity and reliability optimization
3Device complexity
If the processor operates in fixed mode, then device complexity is reduced, but adaptability to different operational requirements deteriorates
Solution Approach 1:
The processor is designed with multi-functionality to operate in both DMR and non-DMR modes, allowing a single device to serve multiple operational requirements. The same hardware infrastructure supports both redundant fault-detection operations and performance-optimized different-task operations, eliminating the need for separate dedicated processors for each mode
Data Source
AI summary
A multi-core processor having a first operation mode in which processors perform the same task and a second operation mode in which the processors perform different tasks includes first and second processors configured to write an operation mode value to a first register or second register when a function called in executed software requests the first or second operation mode, a manager configured to assign core IDs of the first and second processors according to the operation mode value stored in the first register or second register, and a reset controller configured to reset the first and second processors in response to the function, wherein the manager assigns the same core ID to the first and second processors when the operation mode value indicates the first operation mode, and allocates different core IDs to the first and second processors when the operation mode value indicates the second operation mode.