Multi-Core ECU FOTA Sequencing with Hardwired Wakeup Rollback
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Solution Overview
Problem
Firmware over-the-air (FOTA) flash updates in vehicles with multiple processors or processor cores become challenging due to the complexity of managing flash sequences and rollbacks, particularly when a secondary processor is dependent on a primary processor for wake-up, leading to potential system failures and operational disruptions.
Innovation Solution
A FOTA flash update control system with a hybrid control processor (HCP) and an auxiliary HCP, where the HCP performs the update first, followed by the AHCP, and both processors coordinate rollbacks through a hardwired wakeup line to ensure independent operation and successful firmware updates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a secondary processor is dependent on a primary processor for wake-up, then the system can maintain simple wake-up control, but the FOTA flash update process becomes complex and prone to failure
Solution Approach 1:
The patent divides the FOTA flash update process into independent segments for each processor core. Each core receives and executes the flash update independently, with the primary processor managing wake-up for the secondary processor. This segmentation allows the secondary processor to operate autonomously during its update without being blocked by the primary processor's wake-up state, resolving the contradiction between simple wake-up control and reliable updates.
Solution Approach 2:
The primary processor performs preliminary actions by managing the wake-up state of the secondary processor before the FOTA flash update begins. The system ensures the secondary processor is properly awakened and ready to receive its update independently. This preliminary coordination enables both processors to execute updates reliably without interference, maintaining simple wake-up control while improving update reliability.
2Productivity
If multiple processors execute FOTA flash updates simultaneously, then update speed increases, but system stability decreases due to coordination failures
Solution Approach 1:
The patent segments the FOTA flash update execution by processor core, with each core executing its update independently. The primary processor and secondary processor each receive and apply their respective flash updates without requiring simultaneous execution or complex coordination. This independent segmentation maintains system stability while allowing parallel progress on updates, improving overall update speed.
Solution Approach 2:
The system implements feedback mechanisms where each processor core reports the status of its FOTA flash update independently. The primary processor monitors the secondary processor's update status through wake-up signals and coordination protocols. This feedback allows the system to detect and handle coordination issues, maintaining stability while enabling efficient parallel updates that improve productivity.
3Device complexity
If all processors revert to previous firmware simultaneously during rollback, then the rollback process is simple, but system functionality is lost due to coordination failures
Solution Approach 1:
The patent segments the firmware rollback process by processor core, with each core independently reverting to its previous firmware version. The primary processor manages the wake-up and coordination for the secondary processor during rollback, ensuring each core executes its rollback independently. This segmentation maintains simple rollback procedures while ensuring system functionality is preserved through coordinated independent rollbacks.
Solution Approach 2:
The primary processor performs preliminary actions by coordinating the wake-up state and rollback timing for the secondary processor. Before the rollback begins, the primary processor ensures the secondary processor is properly awakened and ready to execute its rollback independently. This preliminary coordination enables simple rollback procedures while maintaining system functionality through proper timing and state management.
Data Source
AI summary
A firmware over-the-air (FOTA) flash update control technique for a multi-core processor of vehicle involves initially performing, by a first processor core, a FOTA flash update during which a second processor core is configured to temporarily disable a stay awake request to the first processor core via a hardwired wakeup line to allow the first processor core to reset, performing, by the second processor core, the FOTA flash update after the first processor core has successfully performed the FOTA flash update, during which the first processor core is configured to temporarily disable a wakeup request to the second processor core via the hardwired wakeup line, and wherein the first and second processor cores are configured to perform a firmware rollback in the event of a failed or incomplete FOTA flash update by one of the first or second processor cores or another related module on a controller area network (CAN).