Multi-Core Processor Heterogeneous Core Scheduling via Primary Mediator

The patent introduces a primary processor core as an intermediary that manages and schedules secondary processor cores. The primary core handles high-level task allocation and coordination, while secondary cores execute specific computing functions. This mediator approach allows heterogeneous cores with different instruction sets and structures to work together without direct complex interactions, resolving the scheduling difficulty while maintaining performance benefits.

The processor system is segmented into primary and secondary processor cores with distinct functional roles. The primary core handles management and scheduling functions, while secondary cores are dedicated to specific computing tasks. This segmentation allows each core type to be optimized independently for its specific function, maintaining high performance while simplifying the overall control architecture.

The patent implements a universal communication interface architecture where the primary processor core can communicate with any secondary processor core through standardized protocols. Despite secondary cores having different instruction sets for specialized processing, they all interface with the primary core through a common communication mechanism, allowing flexible processing while simplifying interface establishment.

The primary processor core serves as an intermediary that translates between different instruction sets and communication protocols. It receives high-level tasks, translates them into appropriate instructions for specific secondary cores, and manages data transfer between cores with different architectures, thereby enabling flexible processing without requiring direct complex communication mechanisms between all core pairs.