Multi-Core IC Structural Scan Testing via Nested Chains
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Solution Overview
Problem
Complex integrated circuits, such as multi-core microprocessors, pose challenges in structural testing due to their complexity and size, making it difficult to perform functional testing effectively, and existing methods like scan testing and random testing have limitations in controlling and observing internal structures efficiently.
Innovation Solution
The integration of structural scan test hardware in integrated circuits allows for simultaneous testing of multiple logic cores, using time-division multiplexing to output test results from each core on a single output line, enabling concurrent or non-concurrent testing modes to minimize the impact of other hardware functions and improve test efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If structural scan test hardware is integrated into multi-core ICs to enable simultaneous testing of multiple cores, then test productivity and coverage are improved, but device complexity and hardware overhead increase
Solution Approach 1:
The patent implements nested scan chains where scan elements are embedded within the logic cores themselves rather than being external. Each core contains its own scan infrastructure, allowing cores to be tested independently and simultaneously. This nesting approach enables parallel testing of multiple cores while containing the added complexity within each core's structure rather than requiring external test infrastructure for all cores.
Solution Approach 2:
The patent divides the multi-core IC into independently testable segments by implementing separate scan chains for each core. This segmentation allows each core to be tested in parallel without interfering with others, improving overall test productivity. The test infrastructure is segmented at the core level, enabling simultaneous execution of tests across multiple cores through independent scan chain control.
2Device complexity
If time-division multiplexing is used to output test results from multiple cores on a single output line, then the number of output pins required is reduced, but test result output speed and throughput are limited
Solution Approach 1:
The patent resolves the output pin limitation by transitioning from spatial multiplexing (multiple pins) to temporal multiplexing (time-domain). Instead of requiring separate output pins for each core, the system uses a single output pin that sequentially outputs results from multiple cores in time slots. This dimensional transformation from space to time reduces the physical pin count while maintaining the ability to output results from all cores.
3Reliability
If scan chains are formed by chaining storage elements in test mode, then structural testing coverage is improved, but routing congestion and I/O pin availability are reduced
Solution Approach 1:
The patent eliminates routing congestion by nesting scan elements within the logic cores themselves. Each core contains its own scan chain infrastructure, so scan elements are formed internally rather than requiring external routing. This internal nesting approach provides comprehensive structural testing coverage while avoiding the routing congestion that would result from chaining storage elements across the entire chip using external interconnects.
Data Source
AI summary
Various embodiments of methods and systems for simultaneously testing multiple cores included in an integrated circuit are disclosed. In one embodiment, an integrated circuit may include two or more logic cores. The IC may also include structural scan test hardware coupled to the cores. This structural scan test hardware may be capable of inputting scan test vector data into scan registers associated with each of the logic cores, simultaneously executing a scan test on the logic cores included in the IC, and outputting the results of the scan tests for multiple cores to automated test equipment (ATE) simultaneously. In one embodiment, elements of the results of testing for multiple cores may be interleaved on a single output line such that an element of test result data from each core is present on an input channel to the ATE during each strobe window.