Multi-Core Idle State Optimization for Latency and Power Budget

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Solution Overview

Problem

Portable computing devices face challenges in optimizing core idle states to minimize latency when transitioning back to active states while managing power consumption within an overall power budget, which affects user experience and quality of service, especially during burst loads.

Innovation Solution

A method and system that determine a power budget for portable computing devices, compare aggregate power consumption, and strategically transition cores from one idle state to another based on operating temperature, allowing for reduced latency without exceeding the power budget, thereby improving user experience and quality of service.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of energy

If a core is placed in an idle state with longer latency to save power, then power consumption is reduced, but quality of service deteriorates during burst loads

Engineering Contradiction:
Improvepower consumptionVSAvoidquality of service
Core Design Contradiction:
Loss of energyVSReliability

Solution Approach 1:

The system dynamically transitions cores between different idle states (deep idle state with higher power savings but longer latency, and shallow idle state with lower power savings but shorter latency) based on real-time conditions. The power management module monitors workload patterns and temperature, then selectively places cores in appropriate idle states, making the system's power consumption and latency characteristics adaptive rather than static.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The invention changes the operational parameters of processor cores by introducing multiple idle states with different power consumption levels and latency characteristics. Instead of a single idle state, the system provides a spectrum of idle states that can be selected based on current needs, effectively changing the parameter space available for power management decisions.

Inventive Principle:
Principle #35Parameter changes

2Reliability

If cores are kept in active state to reduce latency, then quality of service is improved, but power consumption increases beyond budget

Engineering Contradiction:
Improvequality of serviceVSAvoidpower consumption
Core Design Contradiction:
ReliabilityVSLoss of energy

Solution Approach 1:

The system dynamically adjusts core states based on workload characteristics and temperature conditions. During low-utilization periods, cores transition to deep idle states for maximum power savings. During burst loads or when temperature permits, cores are kept in shallower idle states or actively scheduled to maintain responsiveness, creating a dynamic balance between power consumption and service quality.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The power management module performs preliminary assessment of workload patterns and temperature conditions before making idle state decisions. By predicting future workload demands and current thermal headroom, the system can proactively place cores in appropriate idle states before power budget constraints or performance requirements become critical issues.

Inventive Principle:
Principle #10Preliminary action

3Adaptability or versatility

If multiple idle states are introduced for optimization, then power management flexibility is improved, but system complexity increases

Engineering Contradiction:
Improvepower management flexibilityVSAvoidsystem complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The power management functionality is segmented into distinct modular components: a power management module that makes decisions, a temperature monitoring module that provides thermal status, and a core scheduling mechanism that executes state transitions. This segmentation allows each component to handle specific aspects of the complexity, making the overall system more manageable and maintainable despite the introduction of multiple idle states.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentEP3022627B1System and method for idle state optimization in a multi-processor system on a chip
Publication Date: 2019.06.19 QUALCOMM INC
  • EP3022627B1 patent drawingFigure 1
  • EP3022627B1 patent drawingFigure 2
  • EP3022627B1 patent drawingFigure 3

AI summary

Various embodiments of methods and systems for idle state optimization in a portable computing device ("PCD") are disclosed. An exemplary method includes comparing an aggregate power consumption level for all processing cores in the PCD to a power budget and, if there is available headroom in the power budget, transitioning cores operating in a first idle state to a different idle state. In doing so, the latency value associated with bringing the transitioned cores out of an idle state and into an active state, should the need arise, may be reduced. The result is that user experience and QoS may be improved as an otherwise idle core in an idle state with a long latency time may be better positioned to quickly transition to an active state and process a workload.