Multi-Core Processor Image Processing Latency Reduction
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Solution Overview
Problem
Current multi-core processor systems face inefficiencies in image processing tasks due to high computational latencies, requiring improved memory and computing resource management for efficient processing of two-dimensional and three-dimensional image data.
Innovation Solution
A multi-core processor system with a plurality of stream processors, each having shared memory and global buffers, where a kernel is distributed for concurrent execution of threads, performing iterative processing steps including forward and backward transforms, and alternating accessing modes between global buffers to reduce latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If computational tasks are performed using conventional multi-core processor systems, then image processing can be accomplished, but computational latencies are high due to inefficient memory and computing resource management
Solution Approach 1:
The processor is divided into multiple independent stream processors (SP0-SP7), each capable of executing kernels concurrently. This segmentation allows parallel processing of image data across multiple cores, reducing computational latency while maintaining high processing efficiency through independent execution units
Solution Approach 2:
The patent introduces a hierarchical memory architecture that adds temporal and spatial dimensions to data access. Global buffers provide temporal buffering across iteration cycles, while local shared memory provides spatial locality for frequently accessed data, creating multi-dimensional optimization that reduces latency without sacrificing productivity
2Ease of operation
If global buffers are accessed frequently by multiple stream processors, then data sharing is improved, but access conflicts and synchronization overhead increase
Solution Approach 1:
Each stream processor is equipped with local shared memory that provides fast, conflict-free access for frequently used data. This localizes data access patterns, reducing global buffer access conflicts while maintaining data sharing capability through controlled global buffer access only when necessary
Solution Approach 2:
Data is pre-loaded into local shared memory from global buffers before kernel execution begins. This preliminary action reduces the need for frequent global buffer accesses during computation, minimizing synchronization overhead while maintaining ease of data sharing
3Productivity
If iterative processing steps are executed concurrently by multiple threads, then processing throughput is improved, but memory access patterns become complex and latency increases
Solution Approach 1:
The global buffers maintain continuous data availability across iteration cycles by pre-loading and buffering data before concurrent thread execution begins. This ensures that iterative processing steps can proceed without interruption, maintaining high throughput while reducing memory access latency through continuous data supply
Solution Approach 2:
The memory hierarchy dynamically adapts to iterative processing patterns by keeping frequently accessed data in local shared memory across iterations. This dynamic data placement optimizes memory access patterns for concurrent thread execution, reducing latency while maintaining high processing throughput
Data Source
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AI summary
A computer-implemented method for image processing on a multi-core processor system (100), the computer-implemented method comprising steps of: distributing a kernel (116) to a plurality of stream processors for concurrently executing a plurality of threads of the kernel by each stream processor (102a, 102b, 102c, 102d), the kernel defining processing steps of an image processing routine in an iterative manner; while each thread of the kernel is concurrently executed by each stream processor, iteratively performing the processing steps defined within the kernel that was distributed to each of the stream processor, wherein each stream processor has a shared memory (104a, 104b, 104c, 104d) locally accessible within the stream processor, and wherein a first global buffer (106a) of the multi-core processor system and a second global buffer (106b) of the multi-core processor system is each accessible to the plurality of stream processors, the processing steps of the image processing routine comprising: (i) computing a forward transform of intermediary input image data to obtain forward transformed data, wherein a first global buffer provides the intermediary input image data, and wherein a shared memory receives the forward transformed data resulting from the forward transform; (ii) processing the forward transformed data to obtain processed data, wherein the shared memory receives the processed data; (iii) computing a backward transform of the processed data to obtain backward transformed data, wherein a second global buffer receives the backward transformed data; and (iv) before the first global buffer provides intermediary input image data, synchronizing the first global buffer between the plurality of stream processors.