Multi-Core Image Processor Kernel Assignment for Energy Efficiency
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Solution Overview
Problem
Traditional image processors either consume high energy due to versatile software development environments or lack versatility due to fixed function hardwired circuitry, with no technology providing a balance between both.
Innovation Solution
A multi-core image processor architecture featuring an array of execution lanes coupled with a two-dimensional shift register array, allowing for efficient processing of image data through kernel-to-kernel connections and buffer units that store and forward data, enabling both versatile application software development and improved power efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If general purpose processor with vector instruction enhancements is used, then versatile application software development platform is provided, but energy consumption per unit of data increases
Solution Approach 1:
The processor is divided into multiple specialized execution units (vector execution unit, scalar execution unit, tensor execution unit) that can be selectively activated based on the specific computational task. This segmentation allows the system to use only the necessary processing resources for each operation, reducing overall energy consumption while maintaining versatility through the ability to handle different data types and operations.
Solution Approach 2:
The processor implements dynamic configuration where execution units can be selectively enabled or disabled based on the workload requirements. The system can adaptively switch between different execution modes (vector, scalar, tensor operations) and adjust the number of active processing elements, allowing optimal energy efficiency for each specific task while preserving full versatility when needed.
2Use of energy by moving object
If fixed function hardwired circuitry is used, then power consumption per unit of data is reduced, but the set of performable tasks becomes limited
Solution Approach 1:
The processor implements a unified architecture where a single processing core can perform multiple types of operations (vector, scalar, and tensor computations) through configurable execution units. This multi-functionality allows the system to achieve high power efficiency similar to fixed-function circuits while maintaining the versatility to perform diverse image processing tasks by reconfiguring the execution units as needed.
Solution Approach 2:
The processor allows dynamic changing of operational parameters such as data precision (e.g., 8-bit, 16-bit, 32-bit), execution mode (vector/scalar/tensor), and processing throughput. By adjusting these parameters based on the specific task requirements, the system can optimize power consumption for each operation while maintaining the ability to perform a wide range of image processing functions.
3Adaptability or versatility
If finer grained data structures with instruction fetch and decode overhead are used, then versatile processing is achieved, but energy consumption increases
Solution Approach 1:
The processor implements preliminary action by pre-fetching and pre-decoding instructions into an instruction cache before they are needed for execution. This allows the instruction fetch and decode overhead to be performed in advance during low-power states, reducing the real-time energy consumption during actual image processing operations while maintaining full instruction set versatility.
Solution Approach 2:
The system uses copying by duplicating critical instruction information into cache structures and using micro-operations that replicate frequently used instruction patterns. This reduces the need for repeated instruction fetch and decode operations, lowering energy consumption while preserving the ability to execute diverse instructions through the cached copies and standardized micro-op sequences.
Data Source
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AI summary
A method is described. The method includes calculating data transfer metrics for kernel-to-kernel connections of a program having a plurality of kernels that is to execute on an image processor. The image processor includes a plurality of processing cores and a network connecting the plurality of processing cores. Each of the kernel-to-kernel connections include a producing kernel that is to execute on one of the processing cores and a consuming kernel that is to execute on another one of the processing cores. The consuming kernel is to operate on data generated by the producing kernel. The method also includes assigning kernels of the plurality of kernels to respective ones of the processing cores based on the calculated data transfer metrics.