Multi-Core I/O Processing with Dynamic Polling and Interrupt Switching

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Solution Overview

Problem

Current I/O processing methods either lead to high CPU load and decreased efficiency due to repetitive polling or slow I/O processing due to CPU interrupts, as they do not effectively balance between polling and interrupt-based detection of reception events.

Innovation Solution

An information processing device with multiple processor cores that execute processes based on priority levels, using polling when possible and CPU interrupts when necessary, to optimize I/O processing speed and efficiency by dynamically switching between these methods based on load conditions.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If polling processing is used to detect reception events, then I/O processing speed is improved, but CPU load increases and efficiency of other processing decreases

Engineering Contradiction:
ImproveI/O processing speedVSAvoidCPU efficiency
Core Design Contradiction:
SpeedVSProductivity

Solution Approach 1:

The system dynamically switches between polling and interrupt-based detection methods based on the execution state of polling processes. When polling is active, interrupt detection is suspended to avoid context switches; when polling is inactive, interrupt detection is enabled to reduce CPU load. This dynamic adaptation resolves the contradiction between I/O speed and CPU efficiency.

Inventive Principle:
Principle #15Dynamics

2Productivity

If CPU interrupt is used to detect reception events, then CPU load is reduced and efficiency of other processing improves, but I/O processing speed decreases due to context switch overhead

Engineering Contradiction:
ImproveCPU efficiencyVSAvoidI/O processing speed
Core Design Contradiction:
ProductivityVSSpeed

Solution Approach 1:

The system dynamically switches between polling and interrupt-based detection methods based on the execution state of polling processes. When polling is active, interrupt detection is suspended to avoid context switches; when polling is inactive, interrupt detection is enabled to reduce CPU load. This dynamic adaptation resolves the contradiction between I/O speed and CPU efficiency.

Inventive Principle:
Principle #15Dynamics

3Reliability

If polling is executed repeatedly by the CPU, then reception events are detected without context switches, but CPU load increases due to repetitive processing

Engineering Contradiction:
ImproveReception event detection reliabilityVSAvoidCPU load
Core Design Contradiction:
ReliabilityVSUse of energy by stationary object

Solution Approach 1:

The system dynamically switches between polling and interrupt-based detection methods based on the execution state of polling processes. When polling is active, interrupt detection is suspended to avoid context switches; when polling is inactive, interrupt detection is enabled to reduce CPU load. This dynamic adaptation resolves the contradiction between I/O speed and CPU efficiency.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The system uses a polling process as an intermediary mechanism to detect reception events. Instead of having the CPU directly execute repetitive polling instructions, a scheduled polling process performs the detection work, allowing the CPU to switch to other tasks when polling is not needed. This intermediary approach reduces direct CPU load while maintaining reliable event detection.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS10545890B2Information processing device, information processing method, and program
Publication Date: 2020.01.28 FUJITSU LTD
  • US10545890B2 patent drawing
  • US10545890B2 patent drawing
  • US10545890B2 patent drawing

AI summary

An information processing device includes a memory, and a plurality of processor cores that access the memory. The plurality of processor cores respectively executes processes to be executed by the plurality of processor cores in accordance with execution priority levels of the processes. When a polling process for repeatedly determining whether reception data for input/output processing is received is underway in one of the plurality of processor cores, the plurality of processor cores respectively executes the input/output processing in response to a determination, made by the polling process, that the reception data have been received, and when the polling process is not underway in any of the plurality of processing cores, the plurality of processor cores respectively executes the input/output processing in response to a processor interrupt issued upon reception of the reception data.