Multi-Core Processor Jitter Control via Dynamic Core Segmentation
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Solution Overview
Problem
Multi-core processors experience non-deterministic code execution timing due to varying frequency ranges, leading to execution jitter, which is undesirable in applications requiring predictable execution times, forcing cores to operate at lower frequencies to control jitter within acceptable ranges.
Innovation Solution
A method involving control logic that configures core operation by disabling or setting to specific states certain cores based on physical location and core configuration parameters to reduce jitter, ensuring consistent execution times across multiple cores.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple cores operate at higher frequencies to increase processing speed, then productivity is improved, but execution jitter increases causing non-deterministic code execution timing
Solution Approach 1:
The patent segments the processor cores into different groups based on their execution timing characteristics. It identifies and isolates specific cores that cause jitter when executing certain code segments, allowing those cores to be separated from the critical timing path. This segmentation enables the remaining cores to maintain deterministic execution timing while still benefiting from high-frequency operation for overall productivity.
Solution Approach 2:
The patent applies local quality by treating different cores differently based on their specific characteristics and the code segments they execute. Instead of uniform treatment, it identifies local problems (specific core-code combinations causing jitter) and applies targeted solutions such as core disabling or frequency adjustment only for those specific cases, while allowing other cores to operate at optimal frequencies.
2Reliability
If execution jitter is controlled by operating cores at lowest frequency, then execution timing predictability is improved, but processing speed decreases
Solution Approach 1:
The patent implements dynamic frequency adjustment where cores can operate at different frequencies depending on the specific code segment being executed and which cores are active. The system dynamically determines optimal frequencies based on real-time conditions rather than using a fixed lowest frequency, allowing high processing speeds when possible while maintaining timing predictability when needed.
Solution Approach 2:
The patent changes operational parameters (frequency, core enablement status) based on detected jitter conditions and code characteristics. By monitoring execution timing and comparing against predicted times, the system adjusts parameters dynamically to reduce jitter only when necessary, rather than permanently operating at lowest frequency, thus maintaining both predictability and productivity.
3Productivity
If all cores are enabled to maximize processing capability, then productivity is improved, but execution jitter increases due to varying core performance
Solution Approach 1:
The patent implements feedback mechanisms that monitor actual execution timing against predicted timing for each code segment. Based on this feedback, the system identifies which cores are causing timing deviations and adjusts their operation accordingly. This feedback loop allows the system to maintain high productivity with all cores enabled while systematically reducing jitter through data-driven adjustments.
Data Source
AI summary
A method of reducing execution jitter includes a processor having several cores and control logic that receives core configuration parameters. Control logic determines if a first set of cores are selected to be disabled. If none of the cores is selected to be disabled, the control logic determines if a second set of cores is selected to be jitter controlled. If the second set of cores is selected to be jitter controlled, the second set of cores is set to a first operating state. If the first set of cores is selected to be disabled, the control logic determines a second operating state for a third set of enabled cores. The control logic determines if the third set of enabled cores is jitter controlled, and if the third set of enabled cores is jitter controlled, the control logic sets the third set of enabled cores to the second operating state.