Multi-Core Computer Architecture for Matrix Inversion
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Solution Overview
Problem
Existing computer architectures are limited by Amdahl's Law, which restricts the performance improvement of parallel processors, leading to inefficiencies in matrix inversion and other algorithms due to stalling of multiplications and sequential parts, despite advancements in microprocessor complexity.
Innovation Solution
The development of a computer architecture that supports simultaneous processes across multiple cores and chips, utilizing log-based multiplication generators and external feedback paths to maintain continuous throughput, eliminating the need for large VLIW memories and optimizing instruction processing locally within each data processor.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If parallel processing is increased to improve performance, then productivity increases, but stalling of multiplications occurs due to sequential parts
Solution Approach 1:
The processor is divided into multiple independent cores (first core, second core, etc.) that can execute different parts of the algorithm simultaneously. Each core handles specific portions of the matrix inversion or FIR filter operations, allowing parallel execution while maintaining continuous multiplication throughput across the system.
Solution Approach 2:
The patent transitions from single-core sequential processing to multi-core parallel processing architecture. By adding the dimension of multiple cores working simultaneously, the system achieves linear performance improvement (2x, 4x, or more) while keeping multiplication units continuously busy through coordinated task distribution across cores.
2Speed
If microprocessor complexity is increased to improve speed, then speed increases, but power consumption increases linearly
Solution Approach 1:
Instead of increasing the complexity of a single microprocessor, the system segments the processing workload across multiple simpler cores. Each core performs basic operations at standard speed, but the combined throughput of multiple cores achieves the desired overall processing speed while power consumption increases sub-linearly compared to a single high-power processor.
Solution Approach 2:
The system changes the architectural parameter from single-processor complexity to multi-processor count. By using Pollack's Rule guidance, the design accepts that power consumption increases with complexity but optimizes by distributing complexity across multiple units rather than concentrating it, achieving better speed-to-power efficiency through parallelism.
3Reliability
If Amdahl's Law is followed with sequential parts, then algorithm correctness is maintained, but performance improvement is limited to asymptotic limit
Solution Approach 1:
The patent segments the algorithm into independent parallelizable components that can be distributed across multiple cores. For matrix inversion, different cores handle different matrix operations simultaneously. For FIR filters, multiple cores process different signal streams in parallel. This segmentation maintains algorithm correctness through proper data dependency management while achieving near-linear performance improvement.
Solution Approach 2:
The architecture ensures continuous useful action by keeping multiplication units busy across all cores without stalling. The system design guarantees that parallel operations continue without interruption by coordinating data flow and computation across cores, eliminating the sequential bottlenecks that would otherwise cause performance limitations under Amdahl's Law.
Data Source
AI summary
A family of computers is disclosed and claimed that supports simultaneous processes from the single core up to multi-chip Program Execution Systems (PES). The instruction processing of the instructed resources is local, dispensing with the need for large VLIW memories. The cores through the PES have maximum performance for Amdahl-compliant algorithms like matrix inversion, because the multiplications do not stall and the other circuitry keeps up. Cores with log based multiplication generators improve this performance by a factor of two for sine and cosine calculations in single precision floating point and have even greater performance for loge and ex calculations. Apparatus specifying, simulating, and/or layouts of the computer (components) are disclosed. Apparatus the computer and/or its components are disclosed.