Multi-Core Memory Controller Atomic Data Write
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Solution Overview
Problem
Existing memory systems face challenges in maintaining data atomicity during write operations, especially in multi-core environments, and in handling sudden power-off scenarios where uncorrectable errors may occur, leading to incomplete or corrupted data.
Innovation Solution
A memory system with a multi-core architecture where a main core divides data into units and allocates them to sub-cores for writing, ensuring that either the entire data unit is written or none is, and includes error detection and recovery mechanisms to maintain atomicity during sudden power-off events by reporting uncorrectable errors and unmapping affected sub-data units.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data is divided into multiple units and written by multiple sub-cores in parallel, then writing speed is improved, but data atomicity cannot be ensured when sudden power-off occurs
Solution Approach 1:
The patent applies preliminary action by writing metadata (data unit identifier, size, offset) to the memory device before actually writing the data content. This metadata serves as a preparatory marker that enables the memory controller to identify and rollback incomplete data units after a sudden power-off event, thus ensuring data atomicity while maintaining parallel writing performance
Solution Approach 2:
The patent implements feedback through the SPQR (Sudden Power-Off Recovery) operation that continuously monitors writing status and detects uncorrectable errors. When an error is detected in one sub-core, the system receives feedback about the failed data unit and triggers a rollback mechanism that coordinates with other sub-cores to maintain atomicity across all parallel writing operations
2Reliability
If the entire data unit is controlled to be written or none written, then data atomicity is maintained, but system complexity increases due to coordination requirements
Solution Approach 1:
The patent segments the data writing process into independent data units, each with its own metadata record containing identifier, size, and offset information. This segmentation allows each sub-core to write data units independently while the memory controller maintains a simplified coordination mechanism through metadata management, reducing the complexity of inter-core coordination
Solution Approach 2:
The patent introduces metadata as an intermediary between the parallel sub-cores and the main control logic. The metadata records act as intermediaries that encode the state and characteristics of each data unit, allowing the memory controller to make atomicity decisions based on simple metadata checks rather than complex real-time coordination between multiple sub-cores
3Reliability
If error detection and rollback mechanisms are implemented, then data integrity is improved, but processing time increases
Solution Approach 1:
The patent applies preliminary action by pre-writing metadata that includes data unit identifier, size, and offset before the actual data writing begins. This preliminary metadata preparation enables rapid error detection and rollback by providing pre-computed reference information, avoiding the need for time-consuming analysis of written data during error recovery
Solution Approach 2:
The patent implements skipping by directly jumping to the offset position of the failed data unit using the pre-stored offset information in metadata. When an uncorrectable error is detected, the system rushes through the rollback process by directly seeking to the correct offset position and overwriting, rather than sequentially checking or partially rolling back through multiple data units, thus minimizing processing time loss
Data Source
AI summary
A memory system, a memory controller and an operating method are disclosed. When a target command which instructs an operation of writing target data to a memory device is received from a host, the target data is divided into data units, and a first data unit among the data units is controlled such that the entire first data unit is written to the memory device or none of the first data unit is written to the memory device. As a consequence, it is possible to write data in specific units in a memory system using a multi-core.