Multi-Core Processor Memory Segmentation for Conflict-Free Parallel Updates
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In information processing apparatuses with multi-core CPUs, performing two update tasks in parallel can lead to data area conflicts, resulting in inappropriate data updates.
Innovation Solution
The apparatus includes a multi-core processor with at least three processor cores and a memory with four data areas, where each processor core performs update tasks on non-object data areas not conflicting with others, using indexes to manage tasks and prevent conflicts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If two update tasks are performed in parallel on multi-core CPU, then processing speed is improved, but data area conflicts occur resulting in inappropriate data updates
Solution Approach 1:
The memory is segmented into multiple data areas (at least four), and update tasks are assigned to specific segments. The first processor core performs update tasks on non-object data areas that are different from those processed by the second processor core, ensuring that parallel operations work on separate memory segments and avoid conflicts.
Solution Approach 2:
An index area is introduced as an intermediary structure that manages and tracks the state of each data area. The index area stores information about which data areas are currently being processed, allowing processor cores to coordinate their operations and select appropriate non-object data areas without direct conflict.
2Reliability
If more data areas are allocated to support parallel update tasks, then conflict resolution is improved, but memory complexity increases
Solution Approach 1:
The index area serves multiple functions: it tracks which data areas are currently being processed, helps processor cores select appropriate non-object data areas, and manages the state information for conflict avoidance. This multi-functional approach avoids the need for additional complex control structures.
Solution Approach 2:
The system changes the state parameters of data areas through the index area, marking them as object or non-object data areas based on current processing status. This parameter-based management allows dynamic control of data area availability without requiring complex physical reconfiguration.
Data Source
AI summary
An information processing apparatus includes a multi-core processor including at least three processor cores, and a memory configured to be accessed by the at least three processor cores. The memory has at least four data areas adapted to store data. The at least three processor cores include a first processor core and a second processor core each configured to perform an update task of updating data stored in the at least four data areas. The first processor core is configured to perform the update task on a non-object data area that is selected from the at least four data areas and is not an object of processing performed by the second processor core.