Multi-Core Semiconductor Memory with Select Circuit for Parallel Access
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Solution Overview
Problem
In multi-port memory systems, simultaneous access requests from multiple input/output ports to the same memory bank lead to delayed access for lower-priority ports, resulting in deteriorated data processing performance, and the inability to individually set access modes for each memory bank limits optimization of data processing performance.
Innovation Solution
A semiconductor apparatus with multiple independently accessible memory cores, a mode information storage unit, and a select circuit that connects each memory core to a bus-interface circuit, allowing for individual operation mode settings and preventing simultaneous access to the same memory core, thus eliminating the need for arbitration and optimizing data processing performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If arbitration is used to handle simultaneous access requests from multiple input/output ports to the same memory bank, then access order is controlled, but data processing performance deteriorates due to delayed access for lower-priority ports
Solution Approach 1:
The memory system is divided into multiple independently accessible memory banks, each capable of handling access requests separately. This segmentation eliminates the need for arbitration when multiple ports access different banks simultaneously, allowing parallel operations without performance degradation.
Solution Approach 2:
The patent introduces a new dimension of independence by allowing each memory bank to be accessed independently with its own control signals. This transforms the single-bus arbitration problem into a multi-dimensional parallel access architecture where multiple access requests can be processed simultaneously across different banks.
2Stability of the object's composition
If the operating mode of memory banks is fixed, then system stability is maintained, but data processing performance optimization is limited
Solution Approach 1:
The patent implements dynamic configurability where each memory bank can independently change its operating mode (burst length, clock frequency, access mode) based on real-time requirements. This dynamic adjustment allows the system to optimize performance for different workloads while maintaining stability through controlled transitions.
Solution Approach 2:
The system allows changing of operational parameters such as burst length, clock frequency, and access mode for each memory bank independently. These parameter changes enable performance optimization without compromising system stability, as each bank can be tuned to its optimal operating point.
3Device complexity
If multiple memory banks share a common bus-interface circuit, then device complexity is reduced, but data processing performance is limited by sequential access
Solution Approach 1:
The system segments the memory architecture into multiple independently accessible banks, each with its own control pathways. This segmentation allows parallel access to multiple banks simultaneously, improving data processing performance while maintaining a relatively simple overall structure through modular design.
Data Source
AI summary
A semiconductor apparatus according to an aspect of the present invention includes first and second bus-interface circuits, a mode information storage unit that stores first and second mode information, the first and second mode information being able to be set through the first bus-interface circuit, a first memory core that operates based on the first mode information, the first memory core being connected to the first bus-interface circuit and supplied with a first clock signal, a second memory core, the second memory core being supplied with a second clock signal and a select circuit that selectively connects the second memory core to the first or second bus-interface circuit based on predetermined switching information, in which the second memory core operates based on the second mode information when the second memory core is connected to the second bus-interface circuit.