Multi-Core Micro-Scheduler for Priority-Driven Interrupt Preemption
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional multi-core system-on-chip architectures face inefficiencies due to the lack of effective preemption management between cores, particularly in scenarios requiring dynamic task prioritization, leading to suboptimal performance and resource utilization.
Innovation Solution
A mechanism is introduced for a multi-core system that offloads function executions to an auxiliary processor while considering task request priority levels, using a main processor to generate and prioritize task requests, communicate them to the auxiliary processor through a shared memory and interrupt signals, and manage preemption based on priority levels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a conventional auxiliary processor executes tasks sequentially without preemption, then the system structure remains simple, but the system responsiveness and resource utilization deteriorate
Solution Approach 1:
The patent implements dynamic task preemption in the auxiliary processor by introducing an execution queue and priority-based scheduling mechanism. The auxiliary processor can now dynamically switch between tasks based on priority levels and interrupt signals, transforming the static sequential execution model into a dynamic preemptive scheduling system that improves responsiveness while maintaining architectural simplicity
Solution Approach 2:
The patent introduces an execution queue as an intermediary data structure between the mailbox receiver and the task execution unit in the auxiliary processor. This queue mediates the task scheduling process by storing task requests with priority levels and managing the preemption logic, allowing the system to achieve complex preemptive scheduling without complicating the core processor architecture
2Device complexity
If task requests are processed without priority levels, then the processing logic remains simple, but the resource utilization and task criticality management deteriorate
Solution Approach 1:
The patent applies local quality by associating different priority levels with different task requests in the execution queue. Each task is assigned a specific priority level (e.g., high, medium, low) that determines its scheduling behavior and preemption characteristics. This allows the system to differentiate and manage tasks with varying criticality requirements without requiring a complete overhaul of the processing logic
Solution Approach 2:
The patent introduces priority level as a new parameter for task requests, transforming the单一的 task processing model into a multi-parameter scheduling system. The priority level parameter enables the auxiliary processor to make intelligent scheduling decisions, select tasks based on urgency, and implement preemption strategies that adapt to different task criticality requirements
3Device complexity
If the auxiliary processor waits for mailbox communication for each task, then the communication protocol remains simple, but the processing efficiency and overhead deteriorate
Solution Approach 1:
The patent implements preliminary action by having the auxiliary processor maintain an execution queue that pre-stores task requests received from the main processor. Instead of waiting for each individual mailbox communication event to trigger task execution, the auxiliary processor can preemptively manage and execute tasks from the queue based on priority and interrupt signals, significantly improving processing efficiency while keeping the mailbox communication protocol simple
Data Source
AI summary
According to an embodiment, a method for scheduling preemption in a multi-core system is proposed. The method includes generating a plurality of task requests, each task request corresponding to a job to be executed by an auxiliary processor and having a respective priority level; storing the plurality of task requests in the shared memory; selecting a first task request from the plurality of task requests stored in the shared memory with a highest priority level; communicating the first task request to the auxiliary processor; suspending an execution of a current task in response to receiving the interrupt signal; retrieving the respective priority level of the first task request; adding the first task request and its respective priority level to an execution queue; and executing a task from the execution queue having a highest priority.