Multi-Core MRAM Configuration for Faster Boot
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing multi-core electronic devices face challenges in boot time, cost, and power consumption due to inefficient memory configurations, particularly in dual-core systems where software transfer times are lengthy, memory duplication is costly, and power consumption is high.
Innovation Solution
Implementing a memory configuration where each core is associated with a primary RAM-type memory capable of retaining data without power, such as MRAM, and a secondary memory for durable storage, allowing software to be transferred to primary memory at boot or update, reducing reliance on external RAM and flash memory.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If software is transferred from external ROM to core RAM at each boot, then the second core can execute software independently, but the boot time increases significantly due to transfer delays
Solution Approach 1:
The patent applies preliminary action by pre-transferring software from external ROM to the second core's RAM before the actual boot process. This allows the second core to execute software immediately without waiting for transfer operations during boot, thereby resolving the contradiction between execution independence and boot time.
2Adaptability or versatility
If each core has its own separate memory configuration (NOR flash + PSRAM or NAND flash + SDRAM), then existing single-core configurations can be reused and software execution is independent, but cost and PCB area increase
Solution Approach 1:
The patent merges the memory configurations of two cores by having them share a common external ROM and a common RAM resource. The first core retains its NOR flash and PSRAM, while the second core shares the external ROM and uses the first core's PSRAM or an external RAM as its executable memory, thereby reducing duplication and lowering cost and PCB area while maintaining configuration reusability.
3Reliability
If each core has its own dedicated RAM for software execution, then software can be executed independently by each core, but power consumption increases due to memory duplication
Solution Approach 1:
The patent applies universality by making the external RAM and PSRAM resources serve multiple functions and multiple cores. The same RAM memory is used by both cores for different purposes: the first core uses it for data storage, while the second core uses it for software execution, thereby eliminating the need for duplicate RAM and reducing power consumption while maintaining execution independence.
4Reliability
If a master-slave memory configuration is used where the first core manages software storage and transfer, then the second core can execute software from its own RAM, but the first core must act as master which impacts security policies
Solution Approach 1:
The patent applies segmentation by separating the roles of the two cores: the first core is dedicated to managing software storage and transfer operations, while the second core is dedicated to software execution. This clear functional segmentation simplifies security policies by defining distinct responsibilities for each core, eliminating the need for complex master-slave authorization mechanisms.
Data Source
Figure 1~2
Figure 3
AI summary
A multi-core device (D), for an electronic equipment (UE), comprises at least two cores (C1, C2) arranged to execute different softwares stored into storing means. At least one (C2) of these cores (C1, C2) is associated with i) a primary memory (PM2) of the RAM type, which is part of the memory means and arranged for durably storing, without power consumption, a software to be executed once it has been transferred and data associated with this software when it is executed, and ii) a memory interface (MI2) coupled to the primary memory (PM2) and arranged to allow this core (C2) to execute this software durably stored into the primary memory (PM2) and to access to the data associated with this software when it is executed.