Multi-Core Processor Dynamic Power Management via Bus Idle Detection
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Solution Overview
Problem
Multi-core processor systems, especially those using the advanced RISC machine (ARM) structure, face limitations in integrating system function modules for advanced power management, leading to restricted power-saving capabilities during runtime as they cannot effectively communicate and enter low power states.
Innovation Solution
A dynamic power management method that involves a boot core and slave cores, where the workload and bus master status are monitored to timely power off or wake up the cores, utilizing a power management unit, PMIO register, processor adjustment unit, and hot-plug unit to adjust frequencies and perform hot-plug operations, allowing the system to enter more power-saving modes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple processor cores are integrated to improve computing capability, then processing performance is improved, but power consumption increases
Solution Approach 1:
The patent implements dynamic power management by allowing processor cores to transition between active and powered-off states based on workload demands. The boot core can dynamically power on slave cores when computing tasks require additional processing capability, and power them off when they are not needed, making the system's power consumption adaptive rather than static.
Solution Approach 2:
The system changes the operational state parameter of processor cores dynamically. By monitoring workload conditions and adjusting whether cores are active or powered off, the system optimizes the balance between computing performance and power consumption, selecting appropriate operational parameters based on real-time demands.
2Device complexity
If system function modules are integrated to reduce hardware cost, then device complexity is reduced, but power management capability is limited
Solution Approach 1:
The boot core serves multiple functions: it acts as the primary processor when slave cores are powered off, manages the power states of slave cores, handles boot operations, and coordinates system-wide power management. This multi-functional design allows the system to achieve advanced power management capabilities without adding dedicated power management hardware modules.
Solution Approach 2:
The system implements self-service power management where the boot core autonomously monitors workload conditions, decides when to power on or off slave cores, and manages the overall power state of the processor system without requiring external power management controllers or complex hardware support.
3Speed
If processor cores remain active during runtime to ensure quick response, then responsiveness is improved, but power consumption increases
Solution Approach 1:
The boot core maintains readiness and can quickly power on slave cores when needed. By keeping the boot core active and capable of rapidly transitioning slave cores from powered-off to active states, the system ensures quick response to workload changes without requiring all cores to remain continuously active, thus balancing responsiveness with power savings.
Data Source
AI summary
A multi-core processor system, a dynamic power management method thereof and a control apparatus thereof are provided. In the method, a workload of a multi-core processor during a runtime stage is obtained. Next, a hot-plug operation is respectively performed on a plurality of slave cores according to the workload and a working state of each slave core. Then, a bus master status and the working state of a boot core are monitored to determine whether to power off the boot core, in which the bus master status is generated by combining a plurality of device statuses reflected by a plurality of peripheral devices. Finally, when the bus master status is determined as idle, the boot core is powered off.