Multi-Core Process Control with Synchronized Three-Segment Cycles

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Solution Overview

Problem

Complex technical processes with multiple independently controllable modules face challenges in achieving short cycle times due to high computing demands, as existing parallelization methods require complex reconfiguration and are not optimized for multi-core processors in industrial automation.

Innovation Solution

A control method that assigns modules to computing cores, allowing for flexible distribution of control tasks across available cores, enabling parallel processing without specific programming for distributed execution, and utilizing a three-segment control cycle for data input, processing, and output, with synchronization between segments to optimize computing time.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of time

If control tasks are distributed to multiple computing cores, then computing time is reduced and cycle time is shortened, but the system requires complex reconfiguration and specific programming for distributed execution

Engineering Contradiction:
Improvecomputing timeVSAvoidreconfiguration complexity
Core Design Contradiction:
Loss of timeVSDevice complexity

Solution Approach 1:

The control program is segmented into multiple independent control tasks that can be executed in parallel on different computing cores. Each control task is assigned to a specific computing core, allowing simultaneous execution without complex inter-core coordination. This segmentation enables the system to distribute computational workload while maintaining simple, modular task structures that don't require complex reconfiguration.

Inventive Principle:
Principle #1Segmentation

2Productivity

If a higher-clocked computer is used, then computing performance is improved, but physical conditions limit further performance increases

Engineering Contradiction:
Improvecomputing performanceVSAvoidperformance scalability
Core Design Contradiction:
ProductivityVSAdaptability or versatility

Solution Approach 1:

Instead of increasing clock speed in a single dimension, the system transitions to parallel processing across multiple computing cores. This dimensional shift from sequential single-core execution to concurrent multi-core execution provides scalable performance improvement without being constrained by physical limits of clock frequency. The system can add more cores to increase performance while maintaining adaptability.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Ease of manufacture

If control programs are designed for single-core execution, then implementation is simpler, but parallel processing capabilities are not utilized

Engineering Contradiction:
Improveprogram implementation simplicityVSAvoidparallel processing efficiency
Core Design Contradiction:
Ease of manufactureVSProductivity

Solution Approach 1:

The controller is designed with universal computing core structures that can execute standard control tasks independently. Each computing core functions as a complete, self-sufficient control unit capable of handling entire control tasks without requiring complex inter-core communication or coordination. This multi-functionality allows simple single-core-like implementation on each core while achieving parallel processing efficiency across the system.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS11327800B2Technical process control in multi-computing-core system
Publication Date: 2022.05.10 BECKHOFF AUTOMATION GMBH
  • US11327800B2 patent drawing
  • US11327800B2 patent drawing
  • US11327800B2 patent drawing

AI summary

To control a technical process comprising a control task for independently controllable modules, modules are each assigned to a computing core on a controller with a plurality of computing cores. The technical process is connected to the controller via at least one communication connection. In a first time segment, the controller provides read-in input data of the modules for the respectively associated computing core. Subsequently, synchronization of the computing cores to which modules are assigned is carried out by the controller. In a second time segment, the computing cores process the input data of the modules to generate output data for the modules, wherein each computing core signals the end of processing. As soon as all computing cores have signaled the end of processing, the output data are provided in a third time segment by the controller in order to be provided to the modules on the communication connection.