Multi-core Processor Dynamic Reconfiguration via Configuration Register
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Solution Overview
Problem
Multi-core microprocessors face challenges in efficient communication and synchronization between cores for tasks like power management, cache management, and debugging, as existing methods lack speed, precision, and system-level transparency.
Innovation Solution
A microprocessor architecture that includes a configuration register to indicate the enablement or disablement of processing cores, allowing each core to read and update the register to manage core status and generate configuration-related values, enabling synchronized operations and dynamic reconfiguration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If semaphores located in system memory are used for inter-core communication, then system-level transparency is achieved, but communication speed and precision are insufficient
Solution Approach 1:
The patent introduces a dedicated configuration register as an intermediary structure between processing cores, replacing the use of general-purpose system memory semaphores. This configuration register serves as a specialized communication medium that provides both the system-level transparency of shared memory and the speed of dedicated hardware structures, resolving the contradiction between transparency and communication speed.
2Productivity
If multiple processing cores operate independently, then processing capacity is increased, but synchronization and coordination between cores become complex
Solution Approach 1:
The patent merges multiple core status indicators into a single configuration register structure that is shared across all processing cores. Instead of requiring separate synchronization mechanisms between each pair of cores, the configuration register provides a unified interface for status indication and coordination, reducing synchronization complexity while maintaining multi-core processing capacity.
3Use of energy by moving object
If processing cores are dynamically enabled or disabled, then power management is improved, but configuration management complexity increases
Solution Approach 1:
The configuration register automatically reflects the enabled/disabled status of processing cores without requiring complex external management. The register structure itself provides the configuration management functionality, with each core's status being self-indicated through the register bits, thereby simplifying power management while maintaining dynamic reconfiguration capability.
Data Source
AI summary
A microprocessor includes a plurality of processing cores and a configuration register configured to indicate whether each of the plurality of processing cores is enabled or disabled. Each enabled one of the plurality of processing cores is configured to read the configuration register in a first instance to determine which of the plurality of processing cores is enabled or disabled and generate a respective configuration-related value based on the read of the configuration register in the first instance. The configuration register is updated to indicate that a previously enabled one of the plurality of processing cores is disabled. Each enabled one of the plurality of processing cores is configured to read the configuration register in a second instance to determine which of the plurality of processing cores is enabled or disabled and generate the respective configuration-related value based on the read of the configuration register in the second instance.