Multi-core Processor Dynamic Reconfiguration via Configuration Register
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Solution Overview
Problem
Multi-core microprocessors face challenges in efficient communication and synchronization between cores for tasks like power management, cache management, and debugging, as existing methods lack speed, precision, and system-level transparency.
Innovation Solution
A microprocessor design with a configuration register that enables each core to read and update configuration parameters, allowing for efficient core enablement/disabling and synchronization through a control unit with hardware semaphores, ensuring precise and simultaneous core operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If semaphores located in system memory are used for core communication, then all cores can access configuration parameters, but the communication speed and precision are insufficient
Solution Approach 1:
The patent introduces a dedicated configuration register accessible through a control unit as an intermediary mechanism between cores. This register serves as a specialized communication channel that provides both the accessibility needed by all cores and the high-speed precision required for configuration operations, resolving the contradiction between general accessibility and specialized performance.
2Ease of operation
If semaphores located in system memory are used for core communication, then all cores can access configuration parameters, but system-level transparency is insufficient
Solution Approach 1:
The control unit acts as an intermediary that provides system-level transparency by managing access to the configuration register and ensuring all cores have accurate, up-to-date information about system state. This intermediary mechanism maintains information consistency across the system while providing controlled access.
Solution Approach 2:
The configuration register system implements feedback mechanisms where cores can read the current state of configuration parameters and update them accordingly. This feedback loop ensures system-level transparency by keeping all cores informed about the current system configuration state through dedicated read operations.
3Adaptability or versatility
If configuration register is updated to disable a core, then core enablement/disabling is achieved, but other enabled cores need to read the updated configuration
Solution Approach 1:
The configuration register provides a continuous, centralized source of configuration information that all enabled cores can access. When a core is disabled, the configuration update is immediately reflected in the register, and other enabled cores can continuously read the updated state without waiting for propagation delays, maintaining continuous useful action across the system.
Solution Approach 2:
The control unit and configuration register serve as an intermediary that immediately reflects configuration changes to all cores. This intermediary mechanism eliminates the need for complex propagation protocols by providing a single source of truth that all cores can read, thus reducing the time loss associated with configuration updates.
Data Source
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AI summary
A microprocessor includes a plurality of processing cores and a configuration register configured to indicate whether each of the plurality of processing cores is enabled or disabled. Each enabled one of the plurality of processing cores is configured to read the configuration register in a first instance to determine which of the plurality of processing cores is enabled or disabled and generate a respective configuration-related value based on the read of the configuration register in the first instance. The configuration register is updated to indicate that a previously enabled one of the plurality of processing cores is disabled. Each enabled one of the plurality of processing cores is configured to read the configuration register in a second instance to determine which of the plurality of processing cores is enabled or disabled and generate the respective configuration-related value based on the read of the configuration register in the second instance.