Multi-Core Processor Chip with Shared Memory Architecture
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Solution Overview
Problem
The existing digital processing devices, such as portable terminals, face challenges with increased size due to multiple processor chips and separate memories, leading to inefficient use of PCB space, complex software management, and complicated communication between processors.
Innovation Solution
A processor chip with integrated multiple processor cores and a data processing method that utilizes a shared memory with partitioned storage areas, allowing efficient access and minimizing data transmission times, thereby optimizing the operating speed and simplifying communication and control between cores.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple processor chips and separate memories are used, then processing functionality is provided, but device size increases and PCB space utilization becomes inefficient
Solution Approach 1:
The patent integrates multiple processor cores (first processor core, second processor core, third processor core) and memory units into a single processor chip. This merging eliminates the need for separate processor chips and external memory components, significantly reducing PCB space while maintaining full processing functionality. The integrated architecture allows all processor cores and memory units to communicate through internal interconnections within the single chip.
2Adaptability or versatility
If multiple independent processor chips are used, then processing capabilities are provided, but software management becomes complex
Solution Approach 1:
The patent implements a unified memory management system that can serve all three processor cores through a single memory controller. This universal memory interface simplifies software management by providing consistent memory access protocols and addressing schemes across all processor cores, eliminating the need for separate software drivers and management routines for each independent processor chip.
3Reliability
If separate memories are used for each processor, then memory access is independent, but memory efficiency decreases
Solution Approach 1:
The patent divides the shared memory into multiple memory units (first memory unit, second memory unit, third memory unit) that can be independently accessed by different processor cores. Each memory unit can be independently controlled and accessed, maintaining access independence while allowing the memory controller to efficiently allocate and manage memory resources across all processor cores, thereby improving overall memory efficiency.
Data Source
AI summary
A chip having integrated multiple processor cores and a data processing method are disclosed. The processor chip includes an MP core (main processor core), an AP core (application processor core) which performs a processing function designated by a control of the MP core, a first SM controller which sets a path such that the MP core is coupled with a shared memory, and a second SM controller which sets a path such that the AP core is coupled with the shared memory. By virtue of the present invention, the number of chips installed can be minimized, to allow efficient utilization of PCB space and enable a compact size for a portable terminal.