Multi-core die reticle modification for inter-core communication
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Solution Overview
Problem
Multi-core microprocessor design faces challenges in power management, signal quality on buses, and scalability, particularly in transitioning between different core configurations efficiently.
Innovation Solution
A method is developed to modify reticle sets for semiconductor wafers to enable the manufacturing of multi-core dies with varying core configurations by adding inter-core communication wires that allow cores to communicate and manage power states, while avoiding the need for additional physical input/output landing pads, thus creating an internal bypass bus to bypass external processor buses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a common bus is used to interconnect multiple cores to a chipset or memory controller, then device complexity is reduced and ease of manufacture is improved, but signal quality deteriorates due to bus congestion and interference
Solution Approach 1:
The patent segments the interconnection system into two parts: a common external bus for chipset/memory controller communication, and private point-to-point inter-core communication channels. This segmentation allows each core to have dedicated communication paths for critical inter-core traffic, improving signal quality while maintaining the simplicity of the shared external bus architecture.
Solution Approach 2:
The patent introduces an intermediary communication mechanism (point-to-point channels) that mediates between cores and the external bus. This intermediary path handles time-critical and high-bandwidth inter-core communication, reducing congestion on the shared external bus and improving overall signal quality and communication reliability.
2Adaptability or versatility
If additional physical input/output landing pads are added to support increased core configurations, then adaptability improves, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The patent makes the reticle set universal by designing it to support multiple core configurations (single-core, dual-core, quad-core, etc.) through software-controlled modifications rather than hardware changes. The same physical reticle infrastructure can be reconfigured via reticle set modifications to produce different core arrangements, eliminating the need for additional landing pads or physical layout changes for each configuration.
Solution Approach 2:
The patent changes the configurable parameters from physical hardware characteristics (landing pad locations, core counts) to software-defined reticle set parameters. By modifying reticle set definitions and compilation options, the system can adapt to different core configurations without altering the physical device structure, thus avoiding increased device complexity.
3Adaptability or versatility
If the reticle set is modified to support multi-core configurations, then adaptability improves, but manufacturing precision requirements increase due to additional inter-core communication wire definitions
Solution Approach 1:
The patent performs preliminary actions by pre-defining all possible inter-core communication wire paths and connections in the reticle set modification process. The reticle compilation tool automatically generates the complete wire routing information before manufacturing, ensuring that all alignment requirements are predetermined and built into the manufacturing data, thereby reducing actual manufacturing precision demands during production.
4Device complexity
If cores communicate via external bus, then device complexity is minimized, but power consumption increases due to longer signal paths and bus contention
Solution Approach 1:
The patent segments communication traffic into two categories: external bus traffic for chipset/memory controller access, and private point-to-point channels for inter-core communication. This segmentation enables cores to communicate locally through shorter, dedicated paths, reducing signal travel distance and associated power consumption while maintaining the simple shared external bus architecture for external communications.
Solution Approach 2:
The patent introduces point-to-point communication channels as an intermediary path between cores, providing a more energy-efficient route for inter-core data exchange compared to the external bus. This intermediary path reduces power consumption by eliminating bus contention and reducing signal path length, while the external bus remains available for external device communications.
Data Source
AI summary
A first reticle set designed for manufacturing dies with a limited number of cores is modified into a second reticle set suitable for manufacturing at least some dies with at least twice as many cores. The first reticle set defines scribe lines to separate the originally defined dies. At least one scribe line is removed from pairs of adjacent but originally distinctly defined dies. Inter-core communication wires are defined to connect the adjacent cores, which are configured to enable the adjacent cores to communicate during operation without connecting to any physical input/output landing pads of the resulting more numerously cored die, which will not carry signals through the inter-core communication wires off the P-core die. The inter-core communication wires may be used for power management coordination purposes or to bypass the external processor bus.