Multi-Core Processor Security Control System for Address Integrity
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Solution Overview
Problem
Existing security control systems for multi-core processors are inadequate in preventing malware attacks that subvert normal program execution by modifying 'jump' or 'return' addresses, particularly as these attacks exploit vulnerabilities in the data segment, which are not effectively addressed by current memory write protection, code signing, and anti-virus software.
Innovation Solution
A security control system that monitors and validates 'jump', 'interrupt', and 'return' addresses across multiple cores, utilizing a dedicated core to enforce secure execution paths and isolate memory spaces, leveraging existing processor structures and potentially additional hardware or software barriers to prevent unauthorized changes, such as those implemented using ARM's TrustZone to separate execution environments and enable fast communication between secure and normal worlds.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If memory write protection, code signing, and anti-virus software are used, then code segment integrity is improved, but data segment protection deteriorates
Solution Approach 1:
The patent divides protection into separate segments: code segment protection through existing mechanisms (write protection, code signing) and data segment protection through new mechanisms (stack canary values, heap metadata protection, data execution prevention). This segmentation allows each segment to be protected by appropriate specialized mechanisms, resolving the contradiction where code protection methods fail to protect data segments.
Solution Approach 2:
The patent introduces intermediary protection mechanisms between the code and data segments. Specifically, it uses canary values as intermediaries in the stack between return addresses and data, and uses metadata structures as intermediaries in the heap to protect data integrity. These intermediaries detect and prevent unauthorized data modifications before they can subvert program execution.
2Ease of operation
If return addresses are stored on the stack with variables, then subroutine execution is simplified, but buffer overflow attacks become possible
Solution Approach 1:
The patent applies preliminary protective actions by inserting canary values (sentinel data) between stack variables and return addresses before subroutine execution. This preliminary placement of protective canaries prevents buffer overflow attacks from reaching and modifying return addresses, while maintaining the simplicity of standard stack-based subroutine execution. The canaries are checked before function returns to detect any overflow attempts.
Solution Approach 2:
The canary value acts as an intermediary element on the stack between the data variables and the return address. This intermediary absorbs or detects buffer overflow attempts, preventing direct access to the return address while maintaining normal subroutine execution flow. The canary serves as a protective barrier that simplifies execution by requiring no special handling during normal operation but providing automatic protection against attacks.
3Reliability
If interrupt service addresses are protected with instructions, then interrupt security is improved, but attack complexity increases
Solution Approach 1:
The patent merges interrupt protection with existing security mechanisms by integrating interrupt service address validation into the overall execution path monitoring system. Instead of creating separate complex protection mechanisms for interrupts, the invention combines interrupt protection with stack canary checks, heap metadata protection, and data execution prevention policies, thereby improving interrupt security while avoiding additional complexity through unified protection architecture.
Solution Approach 2:
The patent implements universal protection mechanisms that serve multiple functions simultaneously. The same data execution prevention policies and address validation mechanisms protect both subroutine returns and interrupt service addresses, as well as general code execution. This multi-functionality improves interrupt security without requiring dedicated complex protection mechanisms, as the universal policies cover all execution path transitions including interrupts.
Data Source
AI summary
A security control system is provided that works as an extra layer of defense as a way to prevent an “attack” that is initiated by modifying either the “jump” or the “return” addresses or both. The principal behind the security control system is to “monitor” the addresses to which the processors would jump, interrupt or return, and identify when these addresses are modified in a manner that does not comply with the normal execution of the processor. In order to do that the security control system uses existing structures in multi-core processors and even anticipates the creation of additional structures to expedite and improve such control.