Multi-Core Processor Security Against DPA and DFA Attacks
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Solution Overview
Problem
Cryptographic computational devices, such as smart cards and mobile phones, are vulnerable to Differential Power Analysis (DPA) and Differential Fault Analysis (DFA) attacks, which compromise security by revealing cryptographic keys and internal states, and existing countermeasures are insufficient in providing comprehensive protection against these non-invasive attacks.
Innovation Solution
A method involving a randomized and redundant execution flow across multiple cores, with a scheduler randomly allocating execution units and introducing delays, generates unpredictable power consumption signals and performs integrity checks to resist DPA and DFA attacks, utilizing software-based countermeasures without requiring external detectors or dedicated hardware.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional cryptographic execution is used, then computational efficiency is maintained, but security against DPA and DFA attacks is compromised
Solution Approach 1:
The cryptographic computation is divided into multiple execution units distributed across multiple cores. Each core executes a portion of the cryptographic algorithm, and the results are combined to produce the final output. This segmentation prevents attackers from analyzing the complete execution trace on a single core, thereby resisting DPA and DFA attacks while maintaining overall computational efficiency through parallel processing.
Solution Approach 2:
The patent introduces dynamic randomization of execution parameters including random delays between execution units, random selection of execution cores, and randomization of intermediate value computations. These dynamic changes make the execution trace unpredictable and prevent attackers from correlating power consumption or fault patterns with specific cryptographic operations, thus enhancing security without permanently sacrificing computational efficiency.
2Reliability
If randomization and redundancy are introduced to resist attacks, then security is enhanced, but execution time increases
Solution Approach 1:
Random delays are introduced periodically between execution units in a controlled manner. These delays are randomized to prevent pattern recognition by attackers but are bounded to avoid excessive execution time. The periodic insertion of these delays disrupts the timing information available to attackers while maintaining acceptable performance by limiting the total delay magnitude.
Solution Approach 2:
The patent dynamically changes execution parameters such as the number of redundant executions, delay durations, and core selection based on security requirements and performance constraints. By adjusting these parameters adaptively, the system achieves adequate security protection against DPA and DFA attacks while minimizing the impact on execution time through optimized parameter selection.
3Reliability
If multiple cores are used with randomized execution, then security against DPA attacks is improved, but system complexity increases
Solution Approach 1:
The patent implements a universal scheduler and execution framework that can operate across multiple different core configurations and cryptographic algorithms. The same randomized execution mechanism works for various cryptographic primitives (AES, RSA, ECC) and can be deployed on different multi-core platform architectures. This universality reduces the need for algorithm-specific or hardware-specific customizations, thereby managing system complexity while providing robust security protection.
Data Source
AI summary
A method to protect computational, in particular cryptographic, devices having multi-core processors from DPA and DFA attacks is disclosed herein. The method implies: Defining a library of execution units functionally grouped into business function related units, security function related units and scheduler function related units; Designating at random one among the plurality of processing cores on the computational device to as a master core for execution of the scheduler function related execution units; and Causing, under control of the scheduler, execution of the library of execution units, so as to result in a randomized execution flow capable of resisting security threats initiated on the computational device.