Multi-Core Shared Resource Architecture for Chip Area Reduction
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Solution Overview
Problem
In multi-core systems, the increasing number of cores leads to a proportional increase in hardware resources, chip area, and cost due to the need for separate hardware resources like registers and memory protection units for each core.
Innovation Solution
Implementing a shared resource architecture where a shared register and memory protection unit are provided independently of the cores, with local registers storing configuration information specific to each core, allowing cores to share resources and reduce redundant hardware.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate hardware resources like registers and memory protection units are provided for each core, then each core can operate independently with dedicated resources, but the total hardware resources, chip area, and cost increase proportionally with the number of cores
Solution Approach 1:
The patent merges the memory protection units into a shared resource that serves multiple cores simultaneously. Instead of having separate MPU instances for each core, a single MPU is shared among multiple cores, reducing the total hardware footprint while maintaining protection functionality for all cores.
Solution Approach 2:
The shared memory protection unit is designed to handle protection tasks for multiple different cores through a unified interface. The MPU can dynamically allocate its protection services to different cores as needed, making a single resource serve multiple functions and multiple cores without requiring dedicated instances for each.
2Adaptability or versatility
If separate hardware resources like registers and memory protection units are provided for each core, then each core has dedicated configuration capabilities, but the hardware resources and cost increase with the number of cores
Solution Approach 1:
The patent combines multiple configuration capabilities into shared resources. The shared register set and shared memory protection unit provide configuration functionality for multiple cores collectively, reducing the total number of hardware components while maintaining the ability to configure and protect memory regions for each individual core.
Solution Approach 2:
The patent introduces intermediary control mechanisms that allow individual cores to access and configure shared resources. Through controlled access interfaces, each core can independently configure memory protection regions and access shared registers, providing adaptability without requiring dedicated hardware instances for each core.
3Productivity
If separate hardware resources are provided for each core, then full resource availability is ensured for each core, but chip area and manufacturing cost increase
Solution Approach 1:
The patent merges identical hardware resources into shared components that serve multiple cores. By combining multiple memory protection units and register sets into shared resources, the total component count is reduced, which directly lowers manufacturing complexity and cost while maintaining the processing capability of each core.
Solution Approach 2:
The patent discards the notion of permanent dedicated hardware instances for each core and instead recovers resources by implementing shared access mechanisms. Resources are dynamically allocated and recovered based on which core needs them at any given time, reducing overall hardware requirements while maintaining productivity.
Data Source
AI summary
According to an embodiment, an information processing apparatus includes a plurality of cores, a shared resource that can be shared by the plurality of cores, and local registers that store configuration information peculiar to the respective cores. The shared resource is provided independently from the plurality of cores. The local registers are provided to the respective cores. This makes it possible to provide an information processing apparatus that can suppress increase in hardware resources even when the number of cores composing a multi-core system increases.