Multi-core Processor Simulation via Timeslice Allocation
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Solution Overview
Problem
Multi-core microprocessor systems face challenges in maximizing performance due to limited parallelism in software applications, requiring significant reprogramming efforts and increased thermal management complexity, which hinders the full utilization of parallel computing resources.
Innovation Solution
A method and system for simulating multiple processors on multiple cores, where processors are allocated to available cores in timeslices, with synchronization mechanisms to ensure data structure consistency and efficient resource utilization, allowing for parallel processing and effective management of inter-processor communication.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple processors are simulated on multiple cores using parallel processing, then simulation speed and productivity are improved, but system complexity and thermal management difficulty increase
Solution Approach 1:
The patent segments the simulation workload into discrete timeslices, dividing the continuous simulation process into manageable time intervals. Each timeslice contains a subset of processor simulations that can be executed in parallel on available cores, enabling systematic parallel processing while maintaining control over system complexity through structured task management.
Solution Approach 2:
The patent implements dynamic allocation of processors to cores based on real-time core availability and simulation progress. The system continuously monitors and reassigns simulation tasks during execution, allowing flexible adaptation to changing system conditions and optimizing resource utilization without requiring static pre-configuration.
2Reliability
If processors are allocated to cores in timeslices with synchronization mechanisms, then data structure consistency and reliability are improved, but processing speed and productivity decrease
Solution Approach 1:
The patent employs periodic synchronization at defined boundaries between timeslices rather than continuous synchronization throughout execution. This approach maintains data structure consistency by synchronizing at regular intervals while allowing uninterrupted parallel processing within each timeslice, thereby preserving both reliability and processing efficiency.
Solution Approach 2:
The system performs preliminary allocation and setup of simulation tasks before executing the parallel processing phase. By pre-organizing the timeslice structure and preparing task assignments in advance, the system minimizes the overhead of synchronization and resource management during the actual parallel execution, maintaining high productivity while ensuring consistency.
3Adaptability or versatility
If the number of simulated processors exceeds the number of available cores, then simulation comprehensiveness is improved, but resource utilization efficiency and productivity decrease
Solution Approach 1:
The patent divides the large set of simulated processors into multiple smaller groups, with each group assigned to a specific timeslice. This segmentation allows the system to process more processors than available cores by distributing them across multiple time intervals, maintaining simulation comprehensiveness while ensuring efficient resource utilization within each timeslice through balanced workload distribution.
Solution Approach 2:
The system executes simulation timeslices in periodic succession, with each timeslice processing a subset of processors on available cores. This periodic execution pattern enables the simulation of a comprehensive set of processors exceeding core count by cycling through multiple timeslices, thereby achieving both adaptability and maintained productivity through structured temporal distribution.
Data Source
AI summary
The invention relates to methods of simulation of a plurality of processors running on a plurality of cores, to multi-core microprocessor systems in which such methods may be carried out, and to computer program products configured to perform a simulation of a plurality of processors, running on a plurality of cores. According to a first aspect of the invention, there is provided a method of running a plurality of simulated processors on a plurality of cores, in which simulation of the processors is performed in parallel on the plurality of cores.