Multi-Core SMI Handling via Master Core Segmentation
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Solution Overview
Problem
Multi-core processors experience execution stalls or 'hang' conditions due to 'SMI merging' when multiple System Management Interrupts (SMIs) are generated in close succession, leading to synchronization issues and increased latency in handling SMIs.
Innovation Solution
The processor designates a master core to handle SMIs without waiting for other cores to enter System Management Mode (SMM), detects spurious SMIs, and directs subordinate cores to handle SMIs originating from them, using an SMI status register to track pending SMIs and resume execution quickly.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the processor waits for all cores to enter SMM before handling SMI, then synchronization is maintained, but execution latency increases and productivity decreases
Solution Approach 1:
The patent segments SMI handling into two distinct paths: a fast path for the master core that does not wait for other cores, and a coordinated path for subordinate cores that maintains synchronization when needed. This segmentation allows the master core to handle SMIs with minimal latency while subordinate cores maintain proper synchronization through wait loops and status register checks.
Solution Approach 2:
The master core performs preliminary action by immediately entering SMM and beginning SMI handling without waiting for subordinate cores. The subordinate cores are prepared in advance with wait loops that will automatically detect when the master core has completed SMI handling through the SMI status register, allowing them to resume execution without excessive delays.
2Device complexity
If the processor uses a single master core to handle all SMIs, then SMI handling is simplified, but scalability to multi-core processors is reduced
Solution Approach 1:
The patent implements a universal SMI handling framework that can operate effectively whether there is one core or multiple cores. The master core handles the bulk of SMI processing, while subordinate cores can participate when needed through the coordinated path. This multi-functional approach allows the same hardware architecture to scale from single-core to multi-core configurations without requiring fundamentally different SMI handling logic.
Solution Approach 2:
The SMI status register acts as an intermediary mechanism that coordinates between the master core and subordinate cores. The master core updates this register to indicate SMI handling status, and subordinate cores monitor this register to determine when it is safe to proceed. This intermediary allows multiple cores to cooperate on SMI handling without requiring complex inter-core communication protocols.
3Reliability
If subordinate cores idle in a wait loop, then synchronization is maintained, but execution efficiency and productivity are reduced
Solution Approach 1:
The subordinate cores use feedback from the SMI status register to dynamically adjust their behavior. Instead of idling in a blind wait loop, the subordinate cores continuously monitor the status register for feedback signals from the master core. When the status register indicates that SMI handling is complete, the subordinate cores immediately resume execution, minimizing idle time while maintaining synchronization.
Solution Approach 2:
The subordinate cores maintain continuity of useful action by using efficient wait loop constructs that consume minimal resources while keeping the cores in a ready state. Rather than completely halting execution, the cores continue to monitor system state and can immediately resume productive work when the SMI handling is complete, reducing the effective loss of time.
Data Source
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AI summary
Technologies for system management interrupt ("SMI") handling include a number of processor cores configured to enter a system management mode ("SMM") in response to detecting an SMI. The first processor core to enter SMM and acquire a master thread lock sets an in-progress flag and executes a master SMI handler without waiting for other processor cores to enter SMM. Other processor cores execute a subordinate SMI handler. The master SMI handler may direct the subordinate SMI handlers to handle core-specific SMIs. The multi-core processor may set an SMI service pending flag in response to detecting the SMI, which is cleared by the processor core that acquires the master thread lock. A processor core entering SMM may immediately resume normal execution upon determining the in-progress flag is not set and the service pending flag is not set, to detect and mitigate spurious SMIs. Other embodiments are described and claimed.