Multi-Core Software Packet Forwarding for DOCSIS and PON
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Solution Overview
Problem
Current industry practices rely heavily on hardware solutions like TCAMs and FPGAs for packet processing in CCAP environments, which are inefficient and inflexible, especially in virtual CCAP and PON networks, lacking the scalability and adaptability needed for modern network services.
Innovation Solution
Implementing packet processing using executable software across multiple software cores, leveraging DPDK and zero-locking rings, with specific packet classification and encryption techniques to optimize packet forwarding in both DOCSIS and PON environments, allowing for flexible and efficient operation across different network setups.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If hardware solutions like TCAMs and FPGAs are used for packet processing, then packet forwarding speed is improved, but device complexity and cost increase
Solution Approach 1:
The patent replaces hardware-based packet processing (TCAMs and FPGAs) with software-based processing using multiple CPU cores. This substitution eliminates complex hardware components while achieving comparable or superior packet forwarding performance through parallel software processing, directly resolving the contradiction between speed and device complexity
Solution Approach 2:
The patent divides packet processing into multiple independent software cores that can operate in parallel. Each core handles specific packet classification and forwarding tasks, enabling scalable performance improvement without increasing overall system complexity. This segmentation allows the system to achieve high-speed forwarding through coordinated software threads rather than complex hardware
2Productivity
If hardware solutions are used for packet processing, then processing capability is improved, but adaptability and flexibility deteriorate
Solution Approach 1:
The patent implements dynamic packet processing where software cores can be configured and reconfigured at runtime based on network conditions and service requirements. This dynamic approach allows the system to adapt to changing traffic patterns and service demands while maintaining high processing capability, resolving the contradiction between productivity and adaptability
Solution Approach 2:
The software-based multi-core architecture provides universal packet processing capability that can handle multiple protocols, services, and forwarding policies through software configuration rather than dedicated hardware. This multi-functionality enables the system to maintain high processing capability while being adaptable to diverse network requirements
3Adaptability or versatility
If software-based packet processing is implemented, then adaptability is improved, but processing efficiency may deteriorate due to cache misses and congestion
Solution Approach 1:
The patent optimizes cache utilization by ensuring that packet classification data and forwarding information are localized to specific CPU cores through cache-line locking mechanisms. This local quality approach minimizes cache misses by keeping frequently accessed data in the local cache of the processing core, thereby maintaining high processing efficiency while preserving software adaptability
Solution Approach 2:
The patent introduces zero-locking rings as an intermediary communication mechanism between software cores. These rings enable efficient inter-core communication without requiring traditional locking protocols that would cause congestion and performance degradation. The zero-locking ring acts as a mediator that maintains high throughput while enabling cooperative multi-core processing
Data Source
AI summary
Approaches for a machine comprising multiple CPU cores to process packets transmitted within a network using executable software. One or more packets are processing by advancing those packets through a sequence of two or more stage instances. Each stage instance of the sequence of two or more stage instances corresponds to one stage of a sequence of stages. The packets either carry DOCSIS data and/or is transmitted within a Passive Optical Network (PON). The packets may also be either received from the upstream direction or transmitted in the downstream direction. Each stage instance is restricted from being executed by more than one of the multiple CPU cores. Each stage instance can be executed by any one of the multiple CPU cores.