Multi-Core Storage Controller Parity Recovery
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Solution Overview
Problem
Conventional storage systems face data corruption issues due to double fault conditions during write operations, where a controller reboot and subsequent forced transfer of data and parity can lead to inconsistencies, especially if one drive fails before the write is completed.
Innovation Solution
A storage array configuration using multiple cores, where one core handles IO processing and another core manages data reconstruction and stripe-set preservation, utilizing a solid state device to store data and prevent corruption by reading all stripes to generate new parity during interrupted writes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the controller enters NVSRAM interrupted write mode and reboots, then the controller firmware can regenerate parity for the data stripe, but a data drive may fail before the host retries the write causing potential data corruption
Solution Approach 1:
The patent applies preliminary action by preserving the stripe set state (including old and new data) in non-volatile storage before a potential failure occurs. This allows the system to recover and regenerate parity correctly after a controller reboot without data corruption, as the original state information is already saved.
Solution Approach 2:
The patent uses copying by creating and preserving a copy of the stripe set state (old data, new data, and parity) in non-volatile storage. This copy serves as a backup that can be used to regenerate parity if a drive fails during the write operation, preventing data corruption.
2Productivity
If the controller forces transfer to the surviving controller after reboot, then the next N writes can be implemented using old/new data to generate new parity, but data corruption may be detected due to inconsistency between data and parity
Solution Approach 1:
The patent applies feedback by checking the preserved stripe set state against the current data and parity after a forced transfer. This verification process detects inconsistencies between old/new data and parity, allowing the system to identify and correct potential data corruption before it propagates.
Solution Approach 2:
The patent uses preliminary action by preserving the complete stripe set state (old data, new data, and parity) before the controller reboot. This preserved state serves as a reference for verifying data consistency after the forced transfer, enabling detection and prevention of corruption.
3Productivity
If multiple cores are used to handle IO processing and parity generation, then performance is enhanced, but the system complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the controller into multiple specialized cores: one core handles IO processing while another core handles parity generation and stripe set preservation. This segmentation allows parallel processing of different tasks, enhancing performance while maintaining clear separation of responsibilities.
Solution Approach 2:
The patent uses multi-functionality by designing cores that can perform multiple related tasks: the IO processing core handles both read and write operations, while the second core manages both parity generation and stripe set preservation. This reduces overall system complexity compared to having separate specialized components for each function.
Data Source
AI summary
An apparatus including a storage array, a primary controller, a secondary controller and a solid state device. The storage array may be configured to be accessed by a plurality of controllers. A first of the plurality of the controllers may be configured as the primary controller configured to read and write to and from the storage array during a normal condition. A second of the plurality of the controllers may be configured as the secondary controller configured to read and write to and from the storage array during a fault condition. The solid state device may be configured to (i) store data and (ii) be accessed by the storage array and the secondary controller.