Multi-Core Processor Stripe Power Control
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Solution Overview
Problem
Conventional multi-core processors face challenges in efficiently managing power consumption across processor cores due to shared supply voltage and clock signals, leading to instability and inefficiencies in power profile adjustments based on computational requirements.
Innovation Solution
Implementing a power control block and clock control block to manage independent power profiles for each stripe of processor cores, using level shifters and synchronizers to facilitate communication and stabilize clock signals, and a transition processing routine to manage clock frequency changes, allowing for dynamic voltage and frequency adjustments based on task requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If shared supply voltage and clock signal are used across all processor cores, then device complexity is reduced and interfaces are simplified, but power management efficiency deteriorates and power profile adjustments become unstable
Solution Approach 1:
The patent divides the processor into multiple stripes, where each stripe has independent power control and clock control blocks. This segmentation allows each stripe to manage its own power profile independently, resolving the contradiction by enabling efficient power management while maintaining simplified interfaces through modular organization.
Solution Approach 2:
The patent implements local power control by providing separate power control blocks and clock control blocks for each stripe. This allows different voltage and frequency settings to be applied locally to different stripes based on their specific computational requirements, improving power management efficiency without requiring complex global control interfaces.
2Loss of energy
If dynamic supply voltage and clock speed control is implemented for power management, then power consumption is reduced when computing requirements are low, but instability and inefficiencies occur in power profile adjustments
Solution Approach 1:
By segmenting the processor into stripes with independent control blocks, the patent enables stable dynamic power management. Each stripe can adjust its power profile independently based on local computational demands, avoiding the instability that occurs when attempting to control power globally across all cores.
Solution Approach 2:
The patent implements feedback mechanisms where power control blocks and clock control blocks monitor computational requirements and adjust supply voltage and clock speed accordingly. This feedback control ensures stable power profile adjustments by continuously adapting to actual computing demands rather than making abrupt changes.
3Use of energy by moving object
If independent power profiles are implemented for each stripe, then power management efficiency is improved and optimal voltage/frequency can be achieved, but device complexity increases
Solution Approach 1:
The patent organizes independent power control and clock control blocks into a modular stripe-based architecture. This segmentation improves power management efficiency by allowing independent control of each stripe while managing complexity through standardized modular units that can be replicated across multiple stripes.
Solution Approach 2:
The power control blocks and clock control blocks are designed as universal multi-functional units that can be applied to multiple stripes. Each control block can manage power and clock signals for its associated stripe, and the same design can be replicated across different stripes, improving power management efficiency without proportionally increasing overall system complexity.
Data Source
AI summary
Embodiments of the disclosure generally set forth techniques for handling communication between processor cores. Some example multi-core processors include a first set of processor cores in a first region of the multi-core processor configured to dynamically receive a first supply voltage and a first clock signal, a second set of processor cores in a second region of the multi-core processor configured to dynamically receive a second supply voltage and a second clock signal, and an interface block coupled to the first set of processor cores and the second set of processor cores, wherein the interface block is configured to facilitate communications between the first set of processor cores and the second set of processor cores.