Multi-core Switch Memory Access Controller
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Solution Overview
Problem
In multi-core processing devices, each processing core typically requires multiple connections to memory banks, leading to a high number of physical couplings needed, which is inefficient and limits scalability.
Innovation Solution
A multi-core switch device with a memory access controller that allows multiple processing cores to access multiple memory banks using fewer physical couplings, implemented through time division multiplexing and arbitration to manage access to memory banks, reducing the number of necessary connections from P×M to N, where N is an integer less than P×M.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If each processing core is directly connected to multiple memory banks, then access speed and reliability are improved, but the number of physical couplings increases significantly
Solution Approach 1:
A memory access controller is introduced as an intermediary component between processing cores and memory banks. The controller manages and arbitrates access requests from multiple cores to multiple memory banks, reducing the need for direct physical connections between each core and each memory bank. This mediator approach maintains fast access speeds while significantly reducing the total number of physical couplings required in the system.
Solution Approach 2:
The memory access controller serves multiple functions: it acts as an arbiter for access requests, a router for directing requests to appropriate memory banks, and a manager for coordinating simultaneous accesses. This multi-functional component allows the system to achieve high-speed access to multiple memory banks from multiple processing cores without requiring a proportional increase in physical connections.
2Device complexity
If the number of physical couplings is reduced, then device complexity and manufacturing cost decrease, but access reliability and speed may be compromised
Solution Approach 1:
The memory access controller serves as a reliable intermediary that manages all access requests between processing cores and memory banks. By centralizing the access management function, the system ensures that even with reduced physical couplings, access reliability is maintained through proper arbitration, request queuing, and coordination mechanisms within the controller.
Solution Approach 2:
The memory access controller implements feedback mechanisms to monitor and manage access requests from multiple processing cores. The controller tracks the state of memory banks, manages request priorities, and coordinates access timing to prevent conflicts. This feedback-based control ensures reliable access even with fewer physical connections by intelligently managing the limited communication channels.
Data Source
AI summary
Some of the embodiments of the present disclosure provide a multi-core switch device comprising a plurality of P processing cores for processing packets received from a computer network; a memory comprising a plurality of M memory banks, the plurality of processing cores and the plurality of memory banks being arranged such that the plurality of processing cores have access to multiple memory banks among the plurality of memory banks to perform corresponding memory operations; and a memory access controller coupling the plurality of processing cores to the plurality of memory banks, the memory access controller configured to selectively provide, to each of the plurality of processing cores, access to multiple memory banks among the plurality of memory banks over a number of N physical couplings such that N (i) is an integer and (ii) is less than P times M.