Multi-core Processor Task Assignment via Shared Memory Access
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Solution Overview
Problem
Conventional multi-core processors face complexity in controlling the operating states and task assignment across processor cores, leading to inefficient task processing.
Innovation Solution
A multi-core processor configuration where a first processor core requests task processing from a second processor core, with information stored in a shared memory area and interrupt notifications sent across processor dies, allowing each second processor core to access the memory area used by the first processor core on the same die, facilitating efficient task execution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If a control unit controls the operating state of each core and selects cores for task assignment in conventional heterogeneous multi-core processors, then task processing can be coordinated, but the control complexity and difficulty of managing core states increases
Solution Approach 1:
The patent extracts the control unit's management functions by having processor cores directly monitor their own operating states and autonomously determine task assignment. Each core reads its own state information from memory and makes decisions without requiring complex centralized control, thereby reducing control complexity while maintaining operational capability.
Solution Approach 2:
Processor cores perform self-monitoring of their operating states and autonomously participate in task assignment decisions. The system eliminates the need for a centralized control unit by enabling each core to read its own state information and make independent decisions about task execution, thereby simplifying the overall control architecture.
2Ease of manufacture
If processor cores are distributed across multiple processor dies, then manufacturing cost and complexity are reduced, but communication overhead and task coordination difficulty increase
Solution Approach 1:
The patent implements a universal memory access mechanism that works consistently across all processor dies. Each core uses the same memory reading procedure to access state information regardless of which die it resides on, providing uniform behavior across the distributed system and simplifying communication protocols.
Solution Approach 2:
The memory space serves as an intermediary medium for communication between cores on different processor dies. Instead of requiring direct complex communication links between all cores, the system uses shared memory as a simple intermediary that all cores can read from to exchange state information and coordination data.
Data Source
AI summary
A multi-core processor which includes a plurality of processor dies. The multi-core processor has a first processor core which processes a first task and a second processor core which processes a second task. The first processor core and the second processor core are formed on each of the plurality of processor dies. When the first processor core makes a request for the second task processing in processing the first task, information on the second task is stored in a memory area used by the first processor core and interrupt notification is made to each of the second processor cores provided respectively on the plurality of processor dies. Each of the second processor cores having received the interrupt notification accesses the memory area used by the first processor core provided on the same processor die as the processor die on which the second processor core is provided.