Multi-core Test Processor Architecture for IC Testing Efficiency
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Solution Overview
Problem
Existing integrated circuit test equipment faces high test costs and low test channel utilization due to the use of independent single-core processors for each Device Under Test (DUT), leading to inefficient parallel testing and increased costs for low- and medium-end DUTs.
Innovation Solution
A multi-core test processor architecture is introduced, featuring a Master-Test-Processor (MTP) and Co-Test-Processors (CTPs) that work asynchronously, allowing for concurrent testing and maximizing test channel utilization by distributing test patterns and commands through a command bus system, enabling efficient asynchronous signal match testing across multiple DUTs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If one independent test processor is assigned to each site, then test flexibility and efficiency are improved, but test cost increases and test channel utilization rate decreases
Solution Approach 1:
The test processor is segmented into a master test processor and multiple co-test processors. The master test processor handles overall test coordination and channel management, while co-test processors handle specific test tasks for multiple sites simultaneously. This segmentation allows one physical processor to function as multiple independent test processors, improving efficiency without proportionally increasing cost.
Solution Approach 2:
The master test processor is designed to perform multiple functions: it acts as a coordination controller for the entire test system, manages test channel allocation, and can directly execute test tasks when needed. This multi-functionality reduces the need for dedicated processors for each function, lowering overall system cost while maintaining high test efficiency.
2Adaptability or versatility
If one independent test processor is assigned to each site, then test flexibility is improved, but test channel utilization rate decreases
Solution Approach 1:
The test channel allocation is made dynamic through the master test processor's ability to reallocate channels based on current test requirements. Co-test processors can be dynamically assigned to different site groups depending on test complexity and timing requirements, ensuring optimal channel utilization while adapting to varying test flexibility needs.
Solution Approach 2:
The master test processor serves as an intermediary between the test channel resources and the co-test processors. It manages the allocation and arbitration of test channels, ensuring that channels are efficiently utilized across multiple sites while maintaining the flexibility required for different test scenarios.
3Device complexity
If the entire test system shares one test processor, then test cost is reduced, but test efficiency decreases
Solution Approach 1:
Rather than using a single monolithic test processor, the system segments processing functions into a master test processor for coordination and multiple co-test processors for parallel execution. This segmentation enables concurrent testing of multiple sites, dramatically improving efficiency while keeping the total processor count lower than having one dedicated processor per site.
Solution Approach 2:
The master test processor acts as an intermediary that coordinates between multiple co-test processors and the test channel resources. It manages task distribution, synchronization, and resource allocation, enabling efficient parallel testing without requiring each site to have its own dedicated processor, thus improving efficiency while controlling cost.
Data Source
AI summary
The present disclosure discloses a multi-core test processor, and an integrated circuit test system and method. The multi-core test processor includes a co-test-processor-sync-controller, a master-test-processor, two or more co-test-processors, and a test subsystem command switching device. Several co-test-processors are introduced under the master-test-processor. The master-test-processor will deliver test patterns that require concurrent testing to the co-test-processors for execution, so as to complete test items similar to the asynchronous signal match test. After the co-test-processors complete the test, the master-test-processor continues to carry out the subsequent test. The present disclosure can achieve asynchronous concurrent test on multiple sites and improve the test efficiency. Meanwhile, idling of fewer test channels can be avoided when asynchronous test channels are allocated to each site, thereby improving test channel utilization rate.