Multi-core System Central Transaction Control Dispatcher
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Solution Overview
Problem
Programming multiple processing cores in multi-core systems is complex and burdensome for developers, as conventional approaches require explicit handling of communication between cores, leading to increased programmer workload and complexity.
Innovation Solution
A multi-core system with centralized transaction control, featuring an upper sub-system and a lower sub-system connected via a data path, where the upper sub-system handles high-level protocols and the lower sub-system manages real-time processing, using a system dispatcher to provide transparent operation of slave processing cores and hardware resources.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional multi-core systems are used with explicit communication handling between cores, then processing performance can be improved through multiple cores, but programming complexity and burden increase significantly
Solution Approach 1:
The patent introduces a message bus as an intermediary component that mediates communication between processing cores. Instead of requiring explicit point-to-point communication handling between cores, the message bus provides a standardized interface that simplifies inter-core messaging. The bus includes message queues and routing mechanisms that automatically manage message delivery, reducing the programming burden while maintaining multi-core processing performance.
Solution Approach 2:
The message bus is designed as a universal communication infrastructure that serves multiple processing cores simultaneously. It provides a single, standardized interface for all inter-core communication needs, eliminating the need for separate communication mechanisms between each pair of cores. This multi-functional approach reduces programming complexity while supporting scalable multi-core architectures.
2Productivity
If multiple slave processing cores are added to a multi-core system, then processing capacity increases, but the burden on programmers to manage each core increases
Solution Approach 1:
The patent segments the communication management function by introducing intermediate components including message queues, message routers, and protocol handlers. These segmented components handle specific aspects of inter-core communication independently, allowing programmers to work with simplified interfaces rather than managing all communication details for multiple cores. This segmentation reduces the cognitive load and programming burden while supporting increased processing capacity through multiple slave cores.
3Reliability
If explicit communication handling between processing cores is implemented, then system control precision is improved, but device complexity increases
Solution Approach 1:
The message bus acts as an intermediary that provides structured communication protocols and message routing mechanisms. This intermediary layer ensures reliable and precise control of inter-core communication while abstracting away the complexity of direct core-to-core messaging. The bus includes features such as message prioritization, routing tables, and error handling that maintain control precision without exposing these complexities to programmers.
Data Source
AI summary
There is provided a multi-core system that includes a lower-subsystem including a first processor and a number of slave processing cores. Each of the slave processing cores can be a coprocessor or a digital signal processor. The first processor is configured to control processing on the slave processing cores and includes a system dispatcher configured to control transactions for execution on the slave processing cores. The system dispatcher is configured to generate the transactions to be executed on the slave processing cores. The first processor can include a number of hardware drivers for receiving the transactions from the system dispatcher and providing the transactions to the slave processing cores for execution. The multi-core system can further include an upper sub-system in communication with the lower-subsystem and including a second processor configured to provide protocol processing.