Multi-Core Video Decoder Buffer Management
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Solution Overview
Problem
Existing video decoding systems face challenges in efficiently decoding ultra-high definition television (UHDTV) video streams due to increased pixel bitrate demands, which requires costly and time-consuming redesigns of new systems, necessitating a solution that leverages existing designs for HDTV decoding.
Innovation Solution
A multi-core video decoder architecture that couples multiple single-core video decoders to decode a single bitstream, with a master-slave configuration or shared instruction set, to manage buffer allocation and coordinate decoding jobs, reducing the need for new silicon and enhancing decoding performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a single video decoding system is designed to handle UHDTV bitrate demands, then decoding capability for higher bitrates is achieved, but system redesign cost and time increase significantly
Solution Approach 1:
The patent divides the video decoding task into multiple independent decoding cores (first video decoder, second video decoder, etc.), each capable of handling a portion of the decoding workload. This segmentation allows the system to process UHDTV bitstreams by distributing the computational burden across multiple cores rather than requiring a complete system redesign for higher bitrates.
2Productivity
If multiple video decoding cores are used to handle higher bitrates, then decoding performance is improved, but buffer management complexity increases
Solution Approach 1:
The patent introduces a buffer management mechanism that acts as an intermediary between multiple video decoding cores and the memory system. This buffer management layer coordinates data flow, manages memory allocation, and handles synchronization between cores, thereby simplifying the complexity of managing multiple decoding operations simultaneously.
3Ease of manufacture
If existing HDTV decoding designs are leveraged for UHDTV, then product life cycle is extended and cost is reduced, but decoding speed may be insufficient for higher bitrates
Solution Approach 1:
The patent combines multiple existing single-core video decoder designs into a multi-core decoding system. By merging several proven HDTV decoding cores that can handle lower bitrates individually, the system achieves the necessary throughput for UHDTV bitrates while reusing established, validated design IP blocks, thereby extending product life cycle and reducing development costs.
Data Source
AI summary
A method and apparatus for a multi-core video decoder for decoding a single bitstream are disclosed. The multi-core video decoder comprises a first video decoder configured to receive the bitstream, parse header information to determine buffer management for a plurality decoding jobs based on the header information, and assign decoding jobs based upon the buffer management. A second video decoder configured to receive the bitstream and decode the bitstream based on an assigned decoding job from the first video decoder.