Multi-core Processor Virtualization for Manufacturing Yield
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Solution Overview
Problem
High transistor counts in integrated circuits lead to increased defect opportunities during manufacturing, resulting in low yield and higher costs, making it impractical to design and manufacture processors for each market segment with unique price and performance characteristics.
Innovation Solution
A multiple-core processor with support for multiple virtual processors, where processor cores and cache banks can be configured to form distinct virtual processors, allowing for flexible resource allocation and utilization within a single processor, enabling separate execution of program instructions and efficient management of resources.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a single processor design is used to serve multiple market segments, then manufacturing cost and complexity are reduced, but the ability to provide customized price and performance characteristics for each segment is compromised
Solution Approach 1:
The processor is divided into multiple independently configurable cores that can be selectively activated or deactivated based on market segment requirements. Each core can be independently configured with different cache bank mappings and resource allocations, allowing a single manufactured processor to serve multiple market segments with different performance and price requirements without requiring separate custom designs for each segment.
Solution Approach 2:
The processor incorporates dynamic configuration capabilities through core/bank mapping logic that can be programmed to create different virtual processor configurations. This allows the same physical processor to dynamically adapt its architecture by enabling or disabling specific core/cache bank combinations, providing customized performance characteristics for different market segments while maintaining a single manufacturing design.
2Adaptability or versatility
If multiple separate processor designs are created for different market segments, then customized price and performance characteristics can be provided for each segment, but manufacturing complexity and cost increase significantly
Solution Approach 1:
A single processor design incorporates universal features that can be configured for different market segments through software-controlled core/bank mapping. The same physical processor can function as a low-performance unit for entry-level markets or a high-performance unit for enterprise markets by dynamically configuring which cores and cache banks are active, eliminating the need for multiple separate processor designs while maintaining customized performance characteristics.
Solution Approach 2:
The processor architecture segments its functional units into independently controllable cores and cache banks, allowing flexible combination of these segments to create different virtual processor configurations. This segmentation enables a single design to provide multiple performance tiers for different market segments without increasing design complexity, as the segmentation is achieved through configuration rather than separate hardware designs.
3Productivity
If high transistor counts are used to increase processor functionality, then performance is improved, but the number of defect opportunities during manufacturing increases leading to lower yield
Solution Approach 1:
The processor is designed with more cores and cache banks than the minimum required for basic functionality, allowing defective units to be compensated for by activating only the functional cores. This partial action approach means that even if some cores or cache banks are defective, the processor can still function by using a subset of available resources, thereby maintaining manufacturing yield while supporting high performance when all components are functional.
Solution Approach 2:
The processor allows dynamic changes in the number of active cores and cache banks based on detected functionality. If defects are detected during manufacturing or operation, the core/bank mapping logic can be reconfigured to exclude defective units while maintaining sufficient functionality. This parameter change capability allows the same physical processor to operate at different performance levels depending on the health status of its components, maintaining yield while supporting high performance.
Data Source
AI summary
A multiple-core processor with support for multiple virtual processors. In one embodiment, a processor may include a cache including a number of cache banks, a number of processor cores and core/bank mapping logic coupled to the cache banks and processor cores. During a first mode of processor operation, each of the processor cores may be configurable to access any of the cache banks, and during a second mode of processor operation, the core/bank mapping logic may be configured to implement a plurality of virtual processors within the processor. A first virtual processor may include a first subset of the processor cores and a first subset of the banks, and a second virtual processor may include a second subset of the processor cores and a second subset of the cache banks. Subsets of processor cores and cache banks included in the first and second virtual processors may be distinct.