Multi-Core Processor Voltage and Frequency Optimization
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Solution Overview
Problem
Current multi-core processors face yield bottlenecks due to manufacturing process variations, where some cores do not meet the required frequency specifications, leading to inefficient power consumption and performance optimization.
Innovation Solution
A system where each core in a multi-core processor is connected to a separate power supply voltage, adjustable by a main controller, allowing dynamic real-time adjustments of both supply voltage and clock frequency to optimize core performance and power consumption, ensuring each core operates at or above the specified frequency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single power supply voltage and fixed clock frequency are used for all cores, then the device complexity is reduced, but manufacturing precision and chip yield deteriorate due to process variations
Solution Approach 1:
The patent divides the single power supply system into multiple independent power supply channels, with each core or core group having its own dedicated power supply. This segmentation allows individual voltage adjustment for each core to compensate for manufacturing variations, ensuring all cores meet frequency specifications without requiring complex global adjustments.
Solution Approach 2:
The patent implements local quality control by providing independent voltage control for each core, allowing each core to operate at its optimal voltage level based on its specific performance characteristics. This local adjustment capability enables slower cores to receive higher voltages while faster cores operate at lower voltages, ensuring all cores meet minimum frequency requirements.
2Manufacturing precision
If individual voltage adjustment for each core is implemented, then manufacturing precision and chip yield are improved, but device complexity increases
Solution Approach 1:
The power supply system is segmented into multiple independent channels, each capable of individual voltage adjustment. This segmentation enables precise control over each core's operating voltage, allowing compensation for manufacturing variations while maintaining a manageable architectural structure through modular design.
Solution Approach 2:
The patent implements dynamic voltage adjustment capability, allowing the system to adapt voltage levels in real-time based on core performance characteristics and workload requirements. This dynamic control enables the system to optimize both manufacturing yield and operational efficiency without requiring complex static configurations.
3Device complexity
If fixed clock frequency is used for all cores, then device complexity is reduced, but productivity deteriorates due to cores not meeting frequency specifications
Solution Approach 1:
The patent implements dynamic clock frequency adjustment for each core, allowing individual frequency optimization based on core performance. This enables cores with lower manufacturing variability to operate at higher frequencies while ensuring all cores meet minimum specifications, thereby improving overall chip yield without requiring complex global frequency control.
Solution Approach 2:
The system changes the operating parameters (voltage and frequency) individually for each core based on measured performance characteristics. By adjusting these parameters dynamically, the system maximizes the number of cores that meet specification requirements, improving productivity and chip yield while maintaining manageable system complexity.
4Reliability
If higher voltage is supplied to ensure minimum frequency specification, then reliability is improved, but use of energy increases
Solution Approach 1:
The patent applies local quality control by supplying higher voltage only to specific cores that require it to meet frequency specifications, rather than uniformly increasing voltage for all cores. This targeted approach ensures reliability for cores that need it while minimizing overall energy consumption by keeping voltage low for cores that can operate at lower levels.
Solution Approach 2:
The system dynamically changes voltage parameters for each core based on its performance characteristics and specification compliance status. By adjusting voltage parameters individually rather than uniformly, the system achieves the minimum reliability threshold for each core while optimizing overall energy efficiency through selective voltage application.
Data Source
AI summary
An apparatus, method, and program product for optimizing core performance and power in a multi-core processor. The apparatus includes a multi-core processor coupled to a clock source providing a clock frequency to one or more cores, an independent power supply coupled to each core for providing a supply voltage to each core and a Phase-Locked Loop (PLL) circuit coupled to each core for dynamically adjusting the clock frequency provided to each core. The apparatus further includes a controller coupled to each core and being configured to collect performance data and power consumption data measured for each core and to adjust, using the PLL circuit, a supply voltage provided to a core, such that, the operational core frequency of the core is greater than a specification core frequency preset for the core and, such that, core performance and power consumption is optimized.