Multi-cut via placement in semiconductor integrated circuits
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Solution Overview
Problem
As semiconductor integrated circuits miniaturize, forming single-cut vias becomes challenging, leading to open failures, increased signal delay, and disconnection due to reduced cross-sectional area, which complicates the replacement of single-cut vias with multi-cut vias in complex wiring layouts, affecting device reliability.
Innovation Solution
A semiconductor integrated circuit design that incorporates a multi-cut via pattern with two vias connected in an overlap area, where the interval between the first end and first via differs from the interval between the second end and second via, allowing for multi-cut via placement in areas where only single-cut vias can be arranged, with reduced overhang constraints compared to conventional designs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If single-cut vias are used in conventional wiring layouts, then the wiring layout can be completed, but the device operation reliability is low due to open failures and disconnection
Solution Approach 1:
The patent divides a single via connection into multiple via segments (first via and second via) arranged in a multi-cut pattern. This segmentation allows the connection to be more reliable while fitting into complex wiring layouts where a single via would not fit due to spacing constraints.
Solution Approach 2:
The patent transitions from a single-cut via (one-dimensional connection) to a multi-cut via pattern (two-dimensional arrangement of multiple vias). This dimensional change enables placement in areas where conventional single-cut vias cannot be arranged, thereby improving reliability in complex wiring scenarios.
2Reliability
If multi-cut vias are provided for each connection point to improve reliability, then device operation reliability improves, but the chip area increases
Solution Approach 1:
The patent applies multi-cut via patterns selectively in specific overlap areas where wiring complexity and spacing constraints exist, rather than uniformly across the entire chip. This localized application improves reliability where needed while minimizing overall chip area increase.
Solution Approach 2:
The patent merges the first via and second via into a single multi-cut via pattern structure that occupies the same overlap area, effectively combining multiple connection functions into one compact unit that does not proportionally increase chip area.
3Length of moving object
If the cross-sectional area of via is reduced to accommodate miniaturization, then wiring width is reduced, but open failure occurs and signal delay increases
Solution Approach 1:
The patent segments the via connection into multiple smaller via instances (first via and second via) arranged in parallel. This segmentation allows each individual via to have reduced cross-sectional area for miniaturization while the collective parallel structure maintains sufficient total conductive area to prevent open failures and reduce signal delay.
Solution Approach 2:
The patent changes the via configuration parameter from a single large via to multiple smaller vias in parallel. This parameter change enables miniaturization of individual via cross-sectional area while maintaining or improving overall connection reliability through the parallel arrangement.
4Manufacturing precision
If overhang is provided to ensure manufacturing reliability, then via formation reliability improves, but the spacing constraint becomes tighter making multi-cut via replacement difficult
Solution Approach 1:
The patent uses a multi-cut via pattern that arranges vias in a two-dimensional configuration within the overlap area. This dimensional arrangement allows the design to accommodate overhang requirements for manufacturing reliability while still finding space for multiple vias by utilizing available spacing in different directions.
Data Source
AI summary
A semiconductor integrated circuit includes a first wiring, a second wiring, a third wiring, a fourth wiring, a first overlap area, a second overlap area, a multi-cut via, the multi-cut via including a first via and a second via formed in the first direction, and a single-cut via formed to connect the third wiring to the fourth wiring in the second overlap area. A width of the second portion of the second wiring corresponding to a first direction is longer than a width of the first portion of the second wiring corresponding to the first direction. A distance between the center of the first via and the center of the second via is longer than the width of the first portion of second wiring.