Multi-Cycle Path Testing With Clock-Pattern Enable Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing automatic test pattern generators struggle to effectively test multi-cycle paths in hardware logic networks due to assumptions of single-cycle paths, leading to incomplete fault detection and verification challenges.
Innovation Solution
Implementing a mask controller and input selectors to enable or disable multi-cycle paths based on a clock pattern, allowing the test tool to simulate and test multi-cycle paths as if they have single-cycle closure, thereby generating appropriate test patterns for fault detection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If automatic test pattern generators assume single-cycle paths, then testing is simpler, but multi-cycle paths cannot be effectively tested
Solution Approach 1:
The patent changes the operational parameters of the test pattern generator by introducing a cycle counter and enable signals that track and control multi-cycle path behavior. The cycle counter increments on clock edges and generates enable signals after a predetermined number of cycles, allowing the generator to properly test paths that span multiple clock cycles rather than assuming single-cycle completion.
Solution Approach 2:
The patent introduces intermediary elements including a cycle counter, enable signals, and delay elements that mediate between the test pattern generator and the multi-cycle paths. These intermediaries track the number of clock cycles and control when test patterns are applied and when results are captured, enabling proper testing of multi-cycle paths without requiring fundamental changes to the testing methodology.
2Measurement precision
If multi-cycle paths are tested with accurate timing, then fault detection improves, but testing complexity increases
Solution Approach 1:
The patent segments the testing process into distinct phases controlled by enable signals. The cycle counter divides the multi-cycle path into discrete clock cycle segments, and enable signals activate specific segments for testing. This segmentation allows precise timing control for each segment while maintaining overall system manageability through modular control logic.
Solution Approach 2:
The patent performs preliminary actions by pre-configuring the cycle counter with the predetermined number of cycles required for each multi-cycle path. The enable signals are generated in advance based on this pre-configured information, allowing the testing system to prepare appropriate test patterns before applying them to the multi-cycle paths, thereby reducing runtime complexity.
3Productivity
If all paths are tested simultaneously, then testing is faster, but timing constraints cannot be properly enforced
Solution Approach 1:
The patent implements periodic action through the cycle counter that increments on each clock edge and generates enable signals at regular intervals corresponding to the predetermined number of cycles. This periodic control mechanism allows multiple paths to be tested in an organized sequence, maintaining timing constraint enforcement while achieving efficient parallel testing through systematic periodic activation of different path segments.
Data Source
AI summary
A disclosed technique includes based on a clock pattern, determining an enable configuration for setting enable signals for one or more multi-cycle paths of a hardware logic network; controlling a selector to set the enable configuration for the one or more multi-cycle paths; and executing testing operations for the hardware logic network with the one or more multi-cycle paths enabled according to the enable configuration.