Multi-cycle test generation for circuit simulation
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Solution Overview
Problem
Existing semiconductor testing systems provide overly pessimistic simulations of circuit designs, underestimating performance and requiring increased tester resources and testing time due to large test pattern counts, especially as clock architecture complexity grows.
Innovation Solution
The proposed system employs a method for generating multi-cycle test patterns with reduced unknown values (X-values) and uses source-based circuit simulation to improve accuracy, reducing processor resources and processing time. This involves identifying clock signal pairs and disturb cells to generate test patterns that minimize disturb cells and stagger clock signals within cycles.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional test pattern generation methods are used, then comprehensive fault detection is achieved, but test pattern count increases leading to increased processor resources and testing time
Solution Approach 1:
The patent segments the circuit design into multiple clock cycles, analyzing and generating test patterns for each cycle independently. This segmentation allows the testing process to be broken down into manageable units, reducing the overall complexity and test pattern count while maintaining comprehensive fault detection coverage across the entire circuit.
Solution Approach 2:
The patent performs preliminary analysis of clock signal pairs and identifies disturb cells before test pattern generation. By pre-identifying cells that may be affected by clock disturbances and preparing simulation environments in advance, the system avoids generating excessive test patterns during actual testing, thereby reducing testing time while ensuring reliable fault detection.
2Measurement precision
If traditional simulation methods are used, then circuit design performance is evaluated, but simulation results are overly pessimistic underestimating actual performance
Solution Approach 1:
The patent applies local quality by creating simulation environments that are specifically tailored to each clock cycle and its associated disturb cells. Instead of using a uniform pessimistic simulation approach across the entire circuit, the system locally adapts the simulation parameters and unknown value assignments to match the actual clock signal behavior and cell interconnections, resulting in more accurate performance predictions.
Solution Approach 2:
The patent dynamically changes simulation parameters based on the identified clock signal pairs and disturb cells. By adjusting the assignment of unknown values (X-values) to cells based on their actual clocking relationships and disturbance potential, the simulation produces results that reflect real circuit behavior more accurately, avoiding the overly pessimistic estimates of traditional methods.
3Reliability
If comprehensive test patterns are generated to cover all clock signal interactions, then fault detection coverage is improved, but device complexity and processing requirements increase
Solution Approach 1:
The patent segments the complex clock signal analysis into discrete clock cycles and identifies specific clock signal pairs within each cycle. This segmentation reduces test pattern complexity by focusing on relevant cell interactions within each time window rather than attempting to generate patterns for all possible clock interactions simultaneously, while maintaining comprehensive fault detection coverage.
Solution Approach 2:
The patent extracts and focuses only on the relevant disturb cells that are actually affected by each clock signal pair, rather than including all cells in the circuit. By taking out only the necessary cells for each clock cycle analysis and generating test patterns specifically for those cells, the system reduces test pattern complexity while preserving fault detection coverage for the critical paths.
Data Source
AI summary
A system and method generates test patterns for simulating a circuit design. Generating the test patterns includes determining clock data of the circuit design. The clock data is determined by determining a first clock signal pair from clock signals, and determining a disturb cell based on the first clock signal pair. The disturb cell is electrically coupled to a first clock signal of the first clock signal pair, and to a second cell. The second cell is electrically coupled to a second clock signal of the first clock signal pair, and an input of the second cell is electrically coupled to an output of the disturb cell. A first test pattern is generated based on the clock data and is output to a memory to be used in simulating a circuit design.